Triple 3-input NAND gate

DESCRIPTION The 74LVC10A is a high performance, low power, low voltage, Si gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74LVC10A provides the 3-input NAND function. FEATURES • Wide supply voltage range of 1.2 V to 3.6 V • In accordance with JEDEC standard n

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PHI

Triple 3-input NAND gate

DESCRIPTION The 74LVC10A is a high performance, low power, low voltage, Si gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74LVC10A provides the 3-input NAND function. FEATURES • Wide supply voltage range of 1.2 V to 3.6 V • In accordance with JEDEC standard n

文件：84.61 Kbytes 页数：8 Pages

PHI

PHI

Triple 3-input NAND gate

DESCRIPTION The 74LVC10A is a high performance, low power, low voltage, Si gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74LVC10A provides the 3-input NAND function. FEATURES • Wide supply voltage range of 1.2 V to 3.6 V • In accordance with JEDEC standard n

文件：84.61 Kbytes 页数：8 Pages

PHI

PHI

Triple 3-input NAND gate

1. General description The 74LVC10A provides three 3-input NAND functions. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. 2. Features and benefits • Wide supply voltage range from 1.2 V to

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Triple 3-input NAND gate

DESCRIPTION The 74LVC10A is a high performance, low power, low voltage, Si gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74LVC10A provides the 3-input NAND function. FEATURES • Wide supply voltage range of 1.2 V to 3.6 V • In accordance with JEDEC standard n

文件：84.61 Kbytes 页数：8 Pages

PHI

PHI

Triple 3-input NAND gate

DESCRIPTION The 74LVC10 is a high performance, low power, low voltage, Si gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74LVC10 provides the 3-input NAND function. FEATURES • Wide supply voltage range of 1.2 V to 3.6 V • In accordance with JEDEC standar

文件：108.29 Kbytes 页数：8 Pages

PHI

PHI

Triple 3-input NAND gate

DESCRIPTION The 74LVC10 is a high performance, low power, low voltage, Si gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74LVC10 provides the 3-input NAND function. FEATURES • Wide supply voltage range of 1.2 V to 3.6 V • In accordance with JEDEC standar

文件：108.29 Kbytes 页数：8 Pages

PHI

PHI

Triple 3-input NAND gate

DESCRIPTION The 74LVC10 is a high performance, low power, low voltage, Si gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74LVC10 provides the 3-input NAND function. FEATURES • Wide supply voltage range of 1.2 V to 3.6 V • In accordance with JEDEC standar

文件：108.29 Kbytes 页数：8 Pages

PHI

PHI

Triple 3-input NAND gate

DESCRIPTION The 74LVC10 is a high performance, low power, low voltage, Si gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74LVC10 provides the 3-input NAND function. FEATURES • Wide supply voltage range of 1.2 V to 3.6 V • In accordance with JEDEC standar

文件：108.29 Kbytes 页数：8 Pages

PHI

PHI

Triple 3-input NAND gate

The 74LVC10A provides three 3-input NAND functions.\n Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. • Wide supply voltage range from 1.2 V to 3.6 V\n• Inputs accept voltages up to 5.5 V\n• CMOS low power consumption\n• Direct interface with TTL levels\n• Latch-up performance exceeds 250 mA\n• Complies with JEDEC standard:• JESD8-7A (1.65 V to 1.95 V)\n• JESD8-5A (2.3 V to 2.7 V)\n• JESD8-C/JESD36 ;

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安世