Dual JK flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LVC109 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109. FEATURES • Wide supply voltage range of 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A. • Inputs accept voltages up to 5.5 V • CMOS low power consumption • Direct i

文件：103.16 Kbytes 页数：10 Pages

PHI

PHI

Dual JK flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LVC109 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109. FEATURES • Wide supply voltage range of 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A. • Inputs accept voltages up to 5.5 V • CMOS low power consumption • Direct i

文件：103.16 Kbytes 页数：10 Pages

PHI

PHI

Dual JK flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LVC109 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109. FEATURES • Wide supply voltage range of 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A. • Inputs accept voltages up to 5.5 V • CMOS low power consumption • Direct i

文件：103.16 Kbytes 页数：10 Pages

PHI

PHI

Dual JK flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LVC109 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109. FEATURES • Wide supply voltage range of 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A. • Inputs accept voltages up to 5.5 V • CMOS low power consumption • Direct i

文件：103.16 Kbytes 页数：10 Pages

PHI

PHI

Dual JK flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LVC109 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109. FEATURES • Wide supply voltage range of 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A. • Inputs accept voltages up to 5.5 V • CMOS low power consumption • Direct i

文件：103.16 Kbytes 页数：10 Pages

PHI

PHI