4-to-16 line decoder/demultiplexer with input latches

The 74HC/HCT4514 are 4-to-16 line decoders/demultiplexers having four binary weighted address inputs (A0to A3), with latches, a latch enable input (LE), and an active LOW enable input (E). The 16 outputs (Q0to Q15) are mutually exclusive active HIGH. When LE is HIGH, the selected output is de

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4-to-16 line decoder/demultiplexer with input latches

1. General description The 74HC4514; 74HCT4514 is a 4-to-16 line decoder/demultiplexer having four binary weighted address inputs (A0 to A3), with latches, a latch enable input (LE), an enable input (E) and 16 outputs (Q0 to Q15). When LE is HIGH, the selected output is determined by the data o

文件：276.68 Kbytes 页数：16 Pages

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4-to-16 line decoder/demultiplexer with input latches

1. General description The 74HC4514; 74HCT4514 is a 4-to-16 line decoder/demultiplexer having four binary weighted address inputs (A0 to A3), with latches, a latch enable input (LE), an enable input (E) and 16 outputs (Q0 to Q15). When LE is HIGH, the selected output is determined by the data o

文件：276.68 Kbytes 页数：16 Pages

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4-to-16 line decoder/demultiplexer with input latches

The 74HC/HCT4514 are 4-to-16 line decoders/demultiplexers having four binary weighted address inputs (A0to A3), with latches, a latch enable input (LE), and an active LOW enable input (E). The 16 outputs (Q0to Q15) are mutually exclusive active HIGH. When LE is HIGH, the selected output is de

文件：76.3 Kbytes 页数：9 Pages

PHI

PHI

4-to-16 line decoder/demultiplexer with input latches

The 74HC/HCT4514 are 4-to-16 line decoders/demultiplexers having four binary weighted address inputs (A0to A3), with latches, a latch enable input (LE), and an active LOW enable input (E). The 16 outputs (Q0to Q15) are mutually exclusive active HIGH. When LE is HIGH, the selected output is de

文件：76.3 Kbytes 页数：9 Pages

PHI

PHI

4-to-16 line decoder/demultiplexer with input latches

1. General description The 74HC4514; 74HCT4514 is a 4-to-16 line decoder/demultiplexer having four binary weighted address inputs (A0 to A3), with latches, a latch enable input (LE), an enable input (E) and 16 outputs (Q0 to Q15). When LE is HIGH, the selected output is determined by the data o

文件：276.68 Kbytes 页数：16 Pages

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4-to-16 line decoder/demultiplexer with input latches

1. General description The 74HC4514-Q100 is a 4-to-16 line decoder/demultiplexer having four binary weighted address inputs (A0 to A3), with latches, a latch enable input (LE), an enable input (E) and 16 outputs (Q0 to Q15). When LE is HIGH, the selected output is determined by the data on An.

文件：242.18 Kbytes 页数：14 Pages

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4-to-16 line decoder/demultiplexer with input latches

1. General description The 74HC4514-Q100 is a 4-to-16 line decoder/demultiplexer having four binary weighted address inputs (A0 to A3), with latches, a latch enable input (LE), an enable input (E) and 16 outputs (Q0 to Q15). When LE is HIGH, the selected output is determined by the data on An.

文件：242.18 Kbytes 页数：14 Pages

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4-to-16 line decoder/demultiplexer with input latches; inverting

1 General description The 74HC4515 is a 4-to-16 line decoder/demultiplexer having four binary weighted address inputs (A0 to A3) with latches, a latch enable input (LE), an enable input (E) and 16 inverting outputs (Q0, to Q15). When LE is HIGH, the selected output is determined by the data on

文件：212.01 Kbytes 页数：14 Pages

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4-to-16 line decoder/demultiplexer with input latches; inverting

FEATURES · Inverting outputs · Output capability: standard · ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT4515 are high-speed Si-gate CMOS devices and are pin compatible with “4515” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4515

文件：67.59 Kbytes 页数：8 Pages

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