3-to-8 line decoder/demultiplexer

1. General description The 74HC238; 74HCT238 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1 and E2 and E3). Every output will be LOW unless E1 and E2 are LOW and E3 is HIGH. This multiple e

文件：267.32 Kbytes 页数：15 Pages

NEXPERIA

安世

3-to-8 line decoder/demultiplexer

1. General description The 74HC238-Q100; 74HCT238-Q100 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1 and E2 and E3). Every output will be LOW unless E1 and E2 are LOW and E3 is HIGH. This

文件：255.08 Kbytes 页数：15 Pages

NEXPERIA

安世

3-to-8 line decoder/demultiplexer

1. General description The 74HC238; 74HCT238 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1 and E2 and E3). Every output will be LOW unless E1 and E2 are LOW and E3 is HIGH. This multiple e

文件：267.32 Kbytes 页数：15 Pages

NEXPERIA

安世

3-to-8 line decoder/demultiplexer

General description 74HC238 and 74HCT238 are high-speed Si-gate CMOS devices and are pin compatible with Low-Power Schottky TTL (LSTTL). The 74HC238/74HCT238 decoders accept three binary weighted address inputs (A0, A1, A2) and when enabled, provide 8 mutually exclusive active HIGH outputs (

文件：120.28 Kbytes 页数：18 Pages

恩XP

丝印：74HC238D；Package：SOIC16；CMOS Digital Integrated Circuits Silicon Monolithic

Functional Description • 3-to-8 Line Decoder General The 74HC238D is a high speed CMOS 3-to-8 DECODER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. When the device is enabled,

文件：216.55 Kbytes 页数：9 Pages

TOSHIBA

东芝

3-to-8 line decoder/demultiplexer

GENERAL DESCRIPTION The 74HC/HCT238 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Demultiplexing capability • Multiple input enable for easy expansion • Ideal for mem

文件：49.61 Kbytes 页数：7 Pages

PHI

PHI

3-to-8 line decoder/demultiplexer

GENERAL DESCRIPTION The 74HC/HCT238 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Demultiplexing capability • Multiple input enable for easy expansion • Ideal for mem

文件：49.61 Kbytes 页数：7 Pages

PHI

PHI

3-to-8 line decoder/demultiplexer

General description 74HC238 and 74HCT238 are high-speed Si-gate CMOS devices and are pin compatible with Low-Power Schottky TTL (LSTTL). The 74HC238/74HCT238 decoders accept three binary weighted address inputs (A0, A1, A2) and when enabled, provide 8 mutually exclusive active HIGH outputs (

文件：120.28 Kbytes 页数：18 Pages

恩XP

3-to-8 line decoder/demultiplexer

1. General description The 74HC238-Q100; 74HCT238-Q100 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1 and E2 and E3). Every output will be LOW unless E1 and E2 are LOW and E3 is HIGH. This

文件：255.08 Kbytes 页数：15 Pages

NEXPERIA

安世

3-to-8 line decoder/demultiplexer

General description 74HC238 and 74HCT238 are high-speed Si-gate CMOS devices and are pin compatible with Low-Power Schottky TTL (LSTTL). The 74HC238/74HCT238 decoders accept three binary weighted address inputs (A0, A1, A2) and when enabled, provide 8 mutually exclusive active HIGH outputs (

文件：120.28 Kbytes 页数：18 Pages

恩XP