Presettable synchronous BCD decade counter; asynchronous reset

GENERAL DESCRIPTION The 74HC/HCT160 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Synchronous counting and loading • Two count enable inputs for n-bit cascading • Positive

文件：63.72 Kbytes 页数：9 Pages

PHI

PHI

Presettable synchronous BCD decade counter; asynchronous reset

1. General description The 74HC160 is a synchronous presettable decade counter with an internal look-ahead carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positivegoing edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset H

文件：256.24 Kbytes 页数：15 Pages

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Presettable synchronous BCD decade counter; asynchronous reset

1. General description The 74HC160 is a synchronous presettable decade counter with an internal look-ahead carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positivegoing edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset H

文件：256.24 Kbytes 页数：15 Pages

NEXPERIA

安世

Presettable synchronous BCD decade counter; asynchronous reset

GENERAL DESCRIPTION The 74HC/HCT160 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Synchronous counting and loading • Two count enable inputs for n-bit cascading • Positive

文件：63.72 Kbytes 页数：9 Pages

PHI

PHI

Presettable synchronous BCD decade counter; asynchronous reset

GENERAL DESCRIPTION The 74HC/HCT160 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Synchronous counting and loading • Two count enable inputs for n-bit cascading • Positive

文件：63.72 Kbytes 页数：9 Pages

PHI

PHI

Presettable synchronous BCD decade counter; asynchronous reset

GENERAL DESCRIPTION The 74HC/HCT160 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Synchronous counting and loading • Two count enable inputs for n-bit cascading • Positive

文件：63.72 Kbytes 页数：9 Pages

PHI

PHI

Presettable synchronous BCD decade counter; asynchronous reset

GENERAL DESCRIPTION The 74HC/HCT160 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Synchronous counting and loading • Two count enable inputs for n-bit cascading • Positive

文件：63.72 Kbytes 页数：9 Pages

PHI

PHI

Presettable synchronous 4-bit binary counter; asynchronous reset

GENERAL DESCRIPTION The 74HC/HCT161 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Synchronous counting and loading • Two count enable inputs for n-bit cascading • Positive

文件：83.61 Kbytes 页数：12 Pages

PHI

PHI

Presettable synchronous 4-bit binary counter; asynchronous reset

1. General description The 74HC161 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positivegoing edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HI

文件：279.75 Kbytes 页数：17 Pages

NEXPERIA

安世

Presettable synchronous 4-bit binary counter; asynchronous reset

1. General description The 74HC161 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positivegoing edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HI

文件：279.75 Kbytes 页数：17 Pages

NEXPERIA

安世