Presettable synchronous 4-bit binary counter; asynchronous reset

GENERAL DESCRIPTION The 74HC/HCT161 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Synchronous counting and loading • Two count enable inputs for n-bit cascading • Positive

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飞利浦

Presettable synchronous 4-bit binary counter; asynchronous reset

1. General description The 74HC161 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positivegoing edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HI

文件：279.75 Kbytes 页数：17 Pages

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安世安世半导体(中国)有限公司

Presettable synchronous 4-bit binary counter; asynchronous reset

GENERAL DESCRIPTION The 74HC/HCT161 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Synchronous counting and loading • Two count enable inputs for n-bit cascading • Positive

文件：83.61 Kbytes 页数：12 Pages

PHI

飞利浦

Presettable synchronous 4-bit binary counter; asynchronous reset

文件：272.51 Kbytes 页数：17 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Presettable synchronous 4-bit binary counter; asynchronous reset

The 74HC161 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW. A LOW at the par • Complies with JEDEC standard no. 7A\n• Input levels:• For 74HC161: CMOS level\n\n• Synchronous counting and loading\n• 2 count enable inputs for n-bit cascading\n• Asynchronous reset\n• Positive-edge triggered clock\n• ESD protection: category:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A ;

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74HC161DB - Presettable synchronous 4-bit binary counter; asynchronous reset

Presettable synchronous 4-bit binary counter; asynchronous reset - The 74HC161 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 ·Complies with JEDEC standard no. 7A\n·Input levels:·For 74HC161: CMOS level;

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Presettable synchronous 4-bit binary counter; asynchronous reset

The 74HC161-Q100 is a synchronous preset table binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW. A LOW at t • Complies with JEDEC standard no. 7A\n• Input levels:• For 74HC161-Q100: CMOS level\n\n• Synchronous counting and loading\n• 2 count enable inputs for n-bit cascading\n• Asynchronous reset\n• Positive-edge triggered clock\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A excee;

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Package：16-SOIC（0.154"，3.90mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 计数器，除法器 描述：IC SYNC 4BIT BINARY COUNT 16SOIC

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Package：16-SSOP（0.209"，5.30mm 宽）；包装：管件 类别：集成电路（IC） 计数器，除法器 描述：IC SYNC 4BIT BINAR COUNTR 16SSOP

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Package：16-SSOP（0.209"，5.30mm 宽）；包装：管件 类别：集成电路（IC） 计数器，除法器 描述：IC SYNC 4BIT BINARY COUNT 16SSOP

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司