Quad buffer/line driver; 3-state

General description The 74HC125; 74HCT125 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A HIGH on nOE causes the outputs to assume a high impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to inter

文件：192.67 Kbytes 页数：17 Pages

恩XP

Quad buffer/line driver; 3-state

1. General description The 74HC125-Q100; 74HCT125-Q100 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A HIGH on nOE causes the outputs to assume a high impedance OFF-state. Inputs include clamp diodes which enable the use of current limiting resi

文件：238.29 Kbytes 页数：13 Pages

NEXPERIA

安世

Quad 3?뭆tate Noninverting Buffers

Quad 3−State Noninverting Buffers High−Performance Silicon−Gate CMOS The MC74HC125A and MC74HC126A are identical in pinout to the LS125 and LS126. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC125A and HC126A n

文件：121.84 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

Quad 3?뭆tate Noninverting Buffers

The 74HC125 is identical in pinout to the LS125. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC125 noninverting buffer is designed to be used with 3−state memory address drivers, clock drivers, and other bus−orien

文件：132.61 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

Quad 3?뭆tate Noninverting Buffers

Quad 3−State Noninverting Buffers High−Performance Silicon−Gate CMOS The MC74HC125A and MC74HC126A are identical in pinout to the LS125 and LS126. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC125A and HC126A n

文件：121.84 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

Quad 3?뭆tate Noninverting Buffers

The 74HC125 is identical in pinout to the LS125. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC125 noninverting buffer is designed to be used with 3−state memory address drivers, clock drivers, and other bus−orien

文件：132.61 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

Quad buffer/line driver; 3-state

General description The 74HC125; 74HCT125 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A HIGH on nOE causes the outputs to assume a high impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to inter

文件：192.67 Kbytes 页数：17 Pages

恩XP

Quad buffer/line driver; 3-state

GENERAL DESCRIPTION The 74HC/HCT125 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: bus driver • ICC category: MSI

文件：42.03 Kbytes 页数：6 Pages

PHI

飞利浦

Quad buffer/line driver; 3-state

GENERAL DESCRIPTION The 74HC/HCT125 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: bus driver • ICC category: MSI

文件：42.03 Kbytes 页数：6 Pages

PHI

飞利浦

Quad buffer/line driver; 3-state

General description The 74HC125; 74HCT125 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A HIGH on nOE causes the outputs to assume a high impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to inter

文件：192.67 Kbytes 页数：17 Pages

恩XP