18-Bit Undershoot/Overshoot Clamp

General Description The 74F1071 is an 18-bit undershoot/overshoot clamp which is designed to limit bus voltages and also to protect more sensitive devices from electrical overstress due to electrostatic discharge (ESD). The inputs of the device aggressively clamp voltage excursions nominally at

文件：91.83 Kbytes 页数：6 Pages

Fairchild

仙童半导体

18-Bit Undershoot/Overshoot Clamp

General Description The 74F1071 is an 18-bit undershoot/overshoot clamp which is designed to limit bus voltages and also to protect more sensitive devices from electrical overstress due to electrostatic discharge (ESD). The inputs of the device aggressively clamp voltage excursions nominally at

文件：91.83 Kbytes 页数：6 Pages

Fairchild

仙童半导体

Dual JK Positive Edge-Triggered Flip-Flop

General Description The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J

文件：79.72 Kbytes 页数：7 Pages

Fairchild

仙童半导体

Positive J-K positive edge-triggered flip-flops

DESCRIPTION The 74F109 is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock (CP) input. The J and K are

文件：85.03 Kbytes 页数：10 Pages

PHI

飞利浦

Dual JK Positive Edge-Triggered Flip-Flop

General Description The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J

文件：79.72 Kbytes 页数：7 Pages

Fairchild

仙童半导体

Dual JK Positive Edge-Triggered Flip-Flop

General Description The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J

文件：79.72 Kbytes 页数：7 Pages

Fairchild

仙童半导体

Dual JK Positive Edge-Triggered Flip-Flop

General Description The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J

文件：79.72 Kbytes 页数：7 Pages

Fairchild

仙童半导体

Triple 3-Input NAND Gate

General Description This device contains three independent gates, each of which performs the logic NAND function.

文件：48.31 Kbytes 页数：4 Pages

Fairchild

仙童半导体

Triple 3-Input NAND Gate

General Description This device contains three independent gates, each of which performs the logic NAND function.

文件：48.31 Kbytes 页数：4 Pages

Fairchild

仙童半导体

Triple 3-Input NAND Gate

General Description This device contains three independent gates, each of which performs the logic NAND function.

文件：48.31 Kbytes 页数：4 Pages

Fairchild

仙童半导体