74ALVT162827DGG数据手册Nexperia中文资料规格书

描述 Description

The 74ALVT162827 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. It is designed for VCC operation at 2.5 V or 3.3 V with I/O compatibility to 5 V.
The 74ALVT162827 20-bit buffers provide high performance bus interface buffering for wide data/address paths or buses carrying parity. They have NOR Output Enables (nOE1, nOE2) for maximum control flexibility.
The 74ALVT162827 is designed with 30 Ω series resistance in both the pull-up and pull-down output structures. This design reduces line noise in applications such as memory address drivers, clock drivers and bus receivers/transmitters.

特性 Features

• Multiple VCC and GND pins minimize switching noise
• 5 V I/O Compatible
• Live insertion/extraction permitted
• 3-State output buffers
• Outputs include series resistance of 30 Ω making external termination resistors unnecessary
• Power-up 3-State
• Output capability: ±12 mA
• Latch-up protection exceeds 500 mA per Jedec Std 17
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model
• Bus hold data inputs eliminate the need for external pull-up resistors to hold unused inputs