74ALVT162821DL数据手册集成电路（IC）的触发器规格书PDF

描述 Description

2.5 V / 3.3 V 20-bit bus-interface D-type flip-flop, positive-edge trigger with 30 Ohm termination resistors (3-State) - The 74ALVT162821 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. It is designed for VCC operation at 2.5V or 3.3V with I/O compatibility to 5V. The 74ALVT162821 has two 10-bit, edge triggered registers, with each register coupled to a 3-State output buffer. The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE) control gates. Each register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop\\'s Q output. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active Low Output Enable (nOE) controls all ten 3-State buffers independent of the register operation. When nOE is Low, the data in the register appears at the outputs. When nOE is Highthe outputs are in high impedance \\

特性 Features

·Outputs include series resistance of 30 Ω making external termination resistors unnecessary
·20-bit positive-edge triggered register
·5 V I/O Compatible
·Multiple VCC and GND pins minimize switching noise
·Live insertion/extraction permitted
·Power-up reset
·Power-up 3-State
·Output capability ±12 mA
·Latch-up protection exceeds 500 mA per Jedec Std 17
·ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model
·Bus hold data inputs eliminate the need for external pull-up resistors to hold unused inputs