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74AHC139PW

Dual 2-to-4 line decoder/demultiplexer

DESCRIPTION The 74AHC/AHCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74AHC/AHCT139 are high-speed, dual 2-to-4 line decoder/demultiplexers. This device has two independent d

文件:582.82 Kbytes 页数:16 Pages

PHI

PHI

PHI

74AHC139PW

Dual 2-to-4 line decoder/demultiplexer

1. General description The 74AHC139; 74AHCT139 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC139; 74AHCT139 is a high-speed, dual 2-to-4 line decoder/demultiplexer. This device

文件:592.18 Kbytes 页数:14 Pages

NEXPERIA

安世

74AHC139PW

Dual 2-to-4 line decoder/demultiplexer

文件:91.25 Kbytes 页数:14 Pages

恩XP

恩XP

74AHC139PWDH

Dual 2-to-4 line decoder/demultiplexer

DESCRIPTION The 74AHC/AHCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74AHC/AHCT139 are high-speed, dual 2-to-4 line decoder/demultiplexers. This device has two independent d

文件:582.82 Kbytes 页数:16 Pages

PHI

PHI

PHI

74AHC139PW-Q100

Dual 2-to-4 line decoder/demultiplexer

文件:696.89 Kbytes 页数:16 Pages

NEXPERIA

安世

74AHC139PW

Dual 2-to-4 line decoder/demultiplexer

The 74AHC139; 74AHCT139 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.\n The 74AHC139; 74AHCT139 is a high-speed, dual 2-to-4 line decoder/demultiplexer. This device has two independent deco • Balanced propagation delays\n• All inputs have Schmitt-trigger actions\n• Inputs accept voltages higher than VCC\n• Input levels:• For 74AHC139: CMOS level\n• For 74AHCT139: TTL level\n\n• ESD protection:• HBM EIA/JESD22-A114E exceeds 2000 V\n• MM EIA/JESD22-A115-A exceeds 200 V\n• CDM EIA/JESD22-;

Nexperia

安世

74AHC139PW-Q100

Dual 2-to-4 line decoder/demultiplexer

The 74AHC139-Q100; 74AHCT139-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A.\n The 74AHC139-Q100; 74AHCT139-Q100 is a high-speed, dual 2-to-4 line decoder/demultiplexer. This device has t • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40°C to +85°C and from -40°C to +125°C\n\n• Balanced propagation delays\n• All inputs have Schmitt-trigger actions\n• Inputs accept voltages higher than VCC\n• Input levels:• For 74AHC139-Q100: CMOS level\n• Fo;

Nexperia

安世

74AHC139PW,112

Package:16-TSSOP(0.173",4.40mm 宽);包装:管件 类别:集成电路(IC) 信号开关,多路复用器,解码器 描述:IC DECODER/DEMUX 1X2:4 16TSSOP

Nexperia USA Inc.

Nexperia USA Inc.

74AHC139PW,118

Package:16-TSSOP(0.173",4.40mm 宽);包装:管件 类别:集成电路(IC) 信号开关,多路复用器,解码器 描述:IC DECODER/DEMUX 1X2:4 16TSSOP

Nexperia USA Inc.

Nexperia USA Inc.

74AHC139PW-Q100J

Package:16-TSSOP(0.173",4.40mm 宽);包装:卷带(TR) 类别:集成电路(IC) 信号开关,多路复用器,解码器 描述:IC DECODER/DEMUX 1X2:4 16TSSOP

Nexperia USA Inc.

Nexperia USA Inc.

技术参数

  • VCC (V):

    2.0 - 5.5

  • Logic switching levels:

    CMOS

  • Output drive capability (mA):

    ± 8

  • tpd (ns):

    3.9

  • Power dissipation considerations:

    low

  • Tamb (°C):

    -40~125

  • Rth(j-a) (K/W):

    122

  • Ψth(j-top) (K/W):

    4.0

  • Rth(j-c) (K/W):

    52

  • Package name:

    TSSOP16

供应商型号品牌批号封装库存备注价格
恩XP
24+
TSSOP
3580
原装现货/15年行业经验欢迎询价
询价
Nexperia
25+
TSSOP
18798
正规渠道,免费送样。支持账期,BOM一站式配齐
询价
恩XP
23+
TSSOP
5000
原装正品,假一罚十
询价
恩XP
16+
NA
8800
诚信经营
询价
PHI
24+
TSSOP
3500
原装现货,可开13%税票
询价
PHI
25+
TSSOP
9500
百分百原装正品 真实公司现货库存 本公司只做原装 可
询价
PHI
25+
TSSOP16
30000
代理全新原装现货,价格优势
询价
PHI
24+
TSSOP
65200
一级代理/放心采购
询价
恩XP
2447
TSSOP
100500
一级代理专营品牌!原装正品,优势现货,长期排单到货
询价
恩XP
1922+
TSSOP
9200
公司原装现货假一罚十特价欢迎来电咨询
询价
更多74AHC139PW供应商 更新时间2026-2-3 8:58:00