3.3V 128K x 8 Asynchronous Static RAM Center Power & Ground Pinout

The 71V124 3.3V CMOS SRAM is organized as 128K x 8. The JEDEC center power/GND pinout reduces noise generation and improves system performance. All bidirectional inputs and outputs of the 71V124 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is u JEDEC revolutionary pinout (center power/GND) for reduced noise\nEqual access and cycle times – Commercial: 10/12/15/20ns – Industrial: 10/12/15/20ns\nOne Chip Select plus one Output Enable pin\nInputs and outputs are LVTTL-compatible\nSingle 3.3V supply\nLow power consumption via chip deselect\nAva;

Renesas

瑞萨

3.3V CMOS Static RAM1 Meg (128K x 8-Bit) Center Power & Ground Pinout

Features ◆ 128K x 8 advanced high-speed CMOS static RAM ◆ JEDEC revolutionary pinout (center power/GND) for reduced noise ◆ Equal access and cycle times – Commercial: 10/12/15ns – Industrial: 10/12/15ns ◆ One Chip Select plus one Output Enable pin ◆ Inputs and outputs are LVTTL-compatible

文件：192.06 Kbytes 页数：9 Pages

RENESAS

瑞萨

3.3V CMOS Static RAM1 Meg (128K x 8-Bit) Center Power & Ground Pinout

Features ◆ 128K x 8 advanced high-speed CMOS static RAM ◆ JEDEC revolutionary pinout (center power/GND) for reduced noise ◆ Equal access and cycle times – Commercial: 10/12/15ns – Industrial: 10/12/15ns ◆ One Chip Select plus one Output Enable pin ◆ Inputs and outputs are LVTTL-compatible

文件：192.06 Kbytes 页数：9 Pages

RENESAS

瑞萨

3.3V CMOS Static RAM1 Meg (128K x 8-Bit) Center Power & Ground Pinout

Features ◆ 128K x 8 advanced high-speed CMOS static RAM ◆ JEDEC revolutionary pinout (center power/GND) for reduced noise ◆ Equal access and cycle times – Commercial: 10/12/15ns – Industrial: 10/12/15ns ◆ One Chip Select plus one Output Enable pin ◆ Inputs and outputs are LVTTL-compatible

文件：192.06 Kbytes 页数：9 Pages

RENESAS

瑞萨

3.3V CMOS Static RAM1 Meg (128K x 8-Bit) Center Power & Ground Pinout

Features ◆ 128K x 8 advanced high-speed CMOS static RAM ◆ JEDEC revolutionary pinout (center power/GND) for reduced noise ◆ Equal access and cycle times – Commercial: 10/12/15ns – Industrial: 10/12/15ns ◆ One Chip Select plus one Output Enable pin ◆ Inputs and outputs are LVTTL-compatible

文件：192.06 Kbytes 页数：9 Pages

RENESAS

瑞萨

3.3V CMOS Static RAM1 Meg (128K x 8-Bit) Center Power & Ground Pinout

Features ◆ 128K x 8 advanced high-speed CMOS static RAM ◆ JEDEC revolutionary pinout (center power/GND) for reduced noise ◆ Equal access and cycle times – Commercial: 10/12/15ns – Industrial: 10/12/15ns ◆ One Chip Select plus one Output Enable pin ◆ Inputs and outputs are LVTTL-compatible

文件：192.06 Kbytes 页数：9 Pages

RENESAS

瑞萨

3.3V CMOS Static RAM1 Meg (128K x 8-Bit) Center Power & Ground Pinout

Features ◆ 128K x 8 advanced high-speed CMOS static RAM ◆ JEDEC revolutionary pinout (center power/GND) for reduced noise ◆ Equal access and cycle times – Commercial: 10/12/15ns – Industrial: 10/12/15ns ◆ One Chip Select plus one Output Enable pin ◆ Inputs and outputs are LVTTL-compatible

文件：192.06 Kbytes 页数：9 Pages

RENESAS

瑞萨

3.3V CMOS Static RAM1 Meg (128K x 8-Bit) Center Power & Ground Pinout

Features ◆ 128K x 8 advanced high-speed CMOS static RAM ◆ JEDEC revolutionary pinout (center power/GND) for reduced noise ◆ Equal access and cycle times – Commercial: 10/12/15ns – Industrial: 10/12/15ns ◆ One Chip Select plus one Output Enable pin ◆ Inputs and outputs are LVTTL-compatible

文件：192.06 Kbytes 页数：9 Pages

RENESAS

瑞萨

3.3V CMOS Static RAM1 Meg (128K x 8-Bit) Center Power & Ground Pinout

Features ◆ 128K x 8 advanced high-speed CMOS static RAM ◆ JEDEC revolutionary pinout (center power/GND) for reduced noise ◆ Equal access and cycle times – Commercial: 10/12/15ns – Industrial: 10/12/15ns ◆ One Chip Select plus one Output Enable pin ◆ Inputs and outputs are LVTTL-compatible

文件：192.06 Kbytes 页数：9 Pages

RENESAS

瑞萨

3.3V CMOS Static RAM1 Meg (128K x 8-Bit) Center Power & Ground Pinout

Features ◆ 128K x 8 advanced high-speed CMOS static RAM ◆ JEDEC revolutionary pinout (center power/GND) for reduced noise ◆ Equal access and cycle times – Commercial: 10/12/15ns – Industrial: 10/12/15ns ◆ One Chip Select plus one Output Enable pin ◆ Inputs and outputs are LVTTL-compatible

文件：192.06 Kbytes 页数：9 Pages

RENESAS

瑞萨