PECL/CMOS TO CMOS CLOCK DIVIDER

文件：134.82 Kbytes 页数：5 Pages

ICST

丝印：558G-01LF；Package：TSSOP；PECL/CMOS TO CMOS CLOCK DRIVER

文件：122.47 Kbytes 页数：6 Pages

IDT

PECL/CMOS to CMOS Clock Driver

The 558-01 accepts a high speed input of either PECL or CMOS, integrates a divider of 1, 2, 3, or 4, and provides four CMOS low skew outputs. The chip also has output enables so that one, three, or all four outputs can be tri-stated. The 558-01 is a member of the IDT Clock Blocks™ family of clock ge • 16-pin TSSOP package\n• Selectable PECL or CMOS inputs\n• Works as a voltage translator\n• Selectable internal divider\n• Operating output voltages of 2.5 V, 3.3 V or 5.0 V\n• Ideal for IA64 designs;

Renesas

瑞萨

LvHSTL to CMOS Clock Divider

The 558-02 accepts a high-speed LVHSTL input and provides four CMOS low skew outputs from a selectable internal divider (divide by 3, divide by 4). The four outputs are split into two banks of two outputs. Each bank has a separate output enable to tri-state the output buffers. The 558-02 is a member 16-pin TSSOP package\nLVHSTL inputs\nAccepts up to 250 MHz input frequency\nFour low skew (<250 ps) outputs\nSelectable internal divider of 3 or 4\nOperating voltage of 3.3 V;

Renesas

瑞萨

Design Kit Tubular Cable Lugs, Standard

WE

魏德米勒

包装：盒 功能：电池电量计，监视器 类别：开发板，套件，编程器 评估板 - 扩展板，子卡 描述：ADAFRUIT MAX17048 LIPOLY / LIION

ADAFRUIT

包装：线轴 类别：电缆，电线 多芯导线 描述：CABLE 2COND 22AWG SHLD 1000'

ALPHAWIRE