丝印：4LN；Package：DSBGA；CDC3RL02 Low Phase-Noise Two-Channel Clock Fan-Out Buffer

1 Features • Low Additive Noise: – –149dBc/Hz at 10kHz Offset Phase Noise – 0.37ps (RMS) Output Jitter • Limited Output Slew Rate for EMI Reduction (1ns to 5ns Rise/Fall Time for 10pF to 50pF Loads) • Adaptive Output Stage Controls Reflection • Regulated 1.8V Externally Available I/O Supply

文件：828.32 Kbytes 页数：23 Pages

TI2

德州仪器

丝印：4LN；Package：DSBGA；CDC3RL02 Low Phase-Noise Two-Channel Clock Fan-Out Buffer

1 Features • Low Additive Noise: – –149dBc/Hz at 10kHz Offset Phase Noise – 0.37ps (RMS) Output Jitter • Limited Output Slew Rate for EMI Reduction (1ns to 5ns Rise/Fall Time for 10pF to 50pF Loads) • Adaptive Output Stage Controls Reflection • Regulated 1.8V Externally Available I/O Supply

文件：828.32 Kbytes 页数：23 Pages

TI2

德州仪器

丝印：4LN；Package：DSBGA；CDC3RL02 Low Phase-Noise Two-Channel Clock Fan-Out Buffer

1 Features • Low Additive Noise: – –149dBc/Hz at 10kHz Offset Phase Noise – 0.37ps (RMS) Output Jitter • Limited Output Slew Rate for EMI Reduction (1ns to 5ns Rise/Fall Time for 10pF to 50pF Loads) • Adaptive Output Stage Controls Reflection • Regulated 1.8V Externally Available I/O Supply

文件：828.32 Kbytes 页数：23 Pages

TI2

德州仪器

丝印：4LN；Package：DSBGA；CDC3RL02 Low Phase-Noise Two-Channel Clock Fan-Out Buffer

1 Features • Low Additive Noise: – –149dBc/Hz at 10kHz Offset Phase Noise – 0.37ps (RMS) Output Jitter • Limited Output Slew Rate for EMI Reduction (1ns to 5ns Rise/Fall Time for 10pF to 50pF Loads) • Adaptive Output Stage Controls Reflection • Regulated 1.8V Externally Available I/O Supply

文件：828.32 Kbytes 页数：23 Pages

TI2

德州仪器

丝印：4LN；Package：DSBGA；CDC3RL02 Low Phase-Noise Two-Channel Clock Fan-Out Buffer

1 Features • Low Additive Noise: – –149dBc/Hz at 10kHz Offset Phase Noise – 0.37ps (RMS) Output Jitter • Limited Output Slew Rate for EMI Reduction (1ns to 5ns Rise/Fall Time for 10pF to 50pF Loads) • Adaptive Output Stage Controls Reflection • Regulated 1.8V Externally Available I/O Supply

文件：828.32 Kbytes 页数：23 Pages

TI2

德州仪器

丝印：4LN；Package：DSBGA；CDC3RL02 Low Phase-Noise Two-Channel Clock Fan-Out Buffer

1 Features • Low Additive Noise: – –149dBc/Hz at 10kHz Offset Phase Noise – 0.37ps (RMS) Output Jitter • Limited Output Slew Rate for EMI Reduction (1ns to 5ns Rise/Fall Time for 10pF to 50pF Loads) • Adaptive Output Stage Controls Reflection • Regulated 1.8V Externally Available I/O Supply

文件：828.32 Kbytes 页数：23 Pages

TI2

德州仪器

丝印：4LN80K5；Package：DPAK；N-channel 800 V, 2.1 Ω typ., 3 A MDmesh™ K5 Power MOSFET in a DPAK package

Features  Industry’s lowest RDS(on) x area  Industry’s best figure of merit (FoM)  Ultra low gate charge  100 avalanche tested  Zener-protected Applications  Switching applications Description This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technolog

文件：814.15 Kbytes 页数：15 Pages

STMICROELECTRONICS

意法半导体

丝印：4LN80K5；Package：TO-220FP；N-channel 800 V, 2.1 Ω typ., 3 A MDmesh™ K5 Power MOSFET in a TO-220FP package

Features  Industry’s lowest RDS(on) * area  Industry’s best FoM (figure of merit)  Ultra low-gate charge  100 avalanche tested  Zener-protected Applications  Switching applications Description This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technolog

文件：719.12 Kbytes 页数：13 Pages

STMICROELECTRONICS

意法半导体

丝印：4LN80K5；Package：TO-220；N-channel 800 V, 2.1 Ω typ.,3 A MDmesh™ K5 Power MOSFET in a TO-220 package

Features  Industry’s lowest RDS(on) * area  Industry’s best figure of merit (FoM)  Ultra low-gate charge  100 avalanche tested  Zener-protected Applications  Switching applications Description This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technolog

文件：718.84 Kbytes 页数：13 Pages

STMICROELECTRONICS

意法半导体

Power MOSFET

文件：1.07618 Mbytes 页数：9 Pages

VBSEMI

微碧半导体