ZL40272中文资料Low Skew, Low Jitter, 12 O/P HCSL Buffer数据手册Microchip规格书

描述 Description

The ZL40272 is 3x12 HCSL/LVDS/LVPECL clock fan out buffer with ultra-low additive jitter of 24fs capable of operating at frequencies up to 1.5 GHz. Using the 12 output ZL40272 and utilizing the individual output pins or I2C interface, you can create hot-swappable PCIe clocktrees. Applications include PCI Express generation 1/2/3/4/5 clock distribution, Intel QPI and UPI distribution, Servers, storage and data centers, switches and routers.

特性 Features

3 to 1 input Multiplexer: Two inputs accept any differential (LVPECL, HCSL, LVDS, SSTL, CML, LVCMOS) or a single ended signal and the third input accepts a crystal or a single ended signal
Twelve differential HCSL/LVDS/LVPECL outputs
Ultra-low additive jitter: 24fs (integration band: 12kHz to 20MHz at 625MHz clock frequency)
Supports clock frequencies from 0 to 1.5GHz
Supports 2.5V or 3.3V power supplies on HCSL/LVDS/LVPECL outputs
Embedded Low Drop Out (LDO) Voltage regulator provides superior Power Supply Noise Rejection
Maximum output to output skew of 50ps
Device controlled via I2C or hardware control pins
Factory configurable default settings via OTP
Transparent for spread spectrum clock
Applications
PCIe Gen1/2/3/4/5 clock distribution
Wired communications: OTN, SONET/SDH, GE, 10 GE, FC and 10G FC
General purpose clock distribution
Low jitter clock trees
Logic translation
Clock and data signal restoration
Wireless communications
High performance microprocessor clock distribution
Test Equipment

简介

ZL40272属于集成电路（IC）的时钟缓冲器驱动器。由制造生产的ZL40272时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。