UPD98501中文资料瑞萨数据手册PDF规格书

FEATURES

• Includes high performance MIPS based 64-bit RISC processor VR4120A

• Can perform RTOS and network middleware (M/W) on the chip

• Includes interface for PROM and flash ROM used for storing boot program

• Includes 32-bit RISC controller, as ATM cell processor

• Software SAR processing by RISC controller affords flexibility for specification update

• Supports CBR/VBR/UBR service classes

• Includes 2-channel 10/100 Mbps Ethernet controllers compliant to IEEE802.3, IEEE802.3u and IEEE802.3x

• Can directly connect external Ethernet PHY device through 3.3-V MII interface

• Includes USB full speed function controller compliant to USB specification 1.1

• Supports operation conforming to the USB Communication Device Class Specification

• Can directly connect 64M-bit and 128M-bit SDRAM as external memory

• Includes 8-bit 33 MHz UTOPIA level 2 interface compliant to ATM Forum af-phy-0039

• Includes boundary scan function (JTAG) compliant to IEEE 1149.1

• Includes Micro Wire interface

• Includes 2-channel general purpose timers

• Using advanced CMOS technology

• Power supply voltage: 3.3 V (I/O), 2.5 V (Core)

• Package 352-pin T-BGA