UPD98412中文资料瑞萨数据手册PDF规格书

FEATURES

• Conforms to ATM FORUM UNI Version 3.1 & Traffic Management 4.0

• Realizes all switch functions with a single chip

• Non-blocking type with switch capacity of 1.5G bps

• UTOPIA Level2 interface allowing you to select bit widths

(4 ports ´ 8 bits, 2 ports ´ 8 bits + 1 port ´ 16 bits, 2 ports ´ 16 bits)

• Various polling modes for UTOPIA Level2 interface

• Can switch 30 logical ports

• Multi-speed (622M bps, 155M bps, 52M bps, 25M bps, etc.)

• Microprocessor connecting port can be set for signaling processing and OAM cell processing

• Supports 16K/32K/64K uni-cast VP/VC and 1K/2K/4K multi-cast VP/VC

• Shared buffer architecture using standard SRAM

• Cell buffer capacity: 12.8K/25.6K/51.2K cells

• Supports four QOS classes (CBR, VBR, ABR, UBR)

• ABR traffic control (binary mode)

• Supports EPD (Early Packet Discard) and PPD (Partial Packet Discard)

• +3.3-V single power source (directly connectable with +5-V TTL level signals)

• Test function: Supports JTAG (IEEE 1149.1)