UPD98409中文资料瑞萨数据手册PDF规格书

FEATURES

• Conforms to ATM Forum

• PCI bus interface (5/3.3 V, 32/64 bits, 33 MHz)

Conforms to PCI Local Bus Specification Revision 2.1

• AAL-5 SAR sublayer and ATM layer functions

• Hardware support of AAL-5 processing (non-AAL-5 processing can be supported in software)

• Supports up to 64 virtual channels (VC) (64-VC control memory)

• Two traffic shapers for transmission scheduling

• MPEG packet transfer engine mitigating the workload of compressed image data transfer by CPU

• Receive FIFO of 12 cells

• PHY device I/F: UTOPIA Level-1 interface (octet/cell level handshake)

• JTAG boundary scan test functions

• 0.35-μm CMOS process, +5/+3.3-V power supply

- Bus interface +5 V : +5/+3.3-V power supply

- Bus interface +3.3 V : +3.3-V single power supply