UPD98408GD-LML中文资料瑞萨数据手册PDF规格书

厂商型号	UPD98408GD-LML
功能描述	MOS INTEGRATED CIRCUIT
文件大小	411.17 Kbytes
页面数量	38 页
生产厂商	Renesas Technology Corp
企业简称	RENESAS【瑞萨】
中文名称	瑞萨科技有限公司官网
原厂标识
数据手册	下载地址一下载地址二到原厂下载
更新时间	2025-6-29 8:08:00
人工找货	UPD98408GD-LML价格和库存，欢迎联系客服免费人工找货

FEATURES

• Provides a 25.6-Mbps ATM PHY (PMD & TC) function for six circuits

• Conforms to the ATM Forum PHY interface specifications (af-phy-0040.000 November 1995).

• UTOPIA Level 2 V1.0 (af-phy-0039.000 June 1995: max. 8 bits/40 MHz) interface

• Three-cell built-in transmit/receive FIFOs for each circuit

• PMD sublayer functions:

(a) Built-in clock recovery.

(b) Built-in equalizer.

• TC sublayer functions:

(a) NRZI encoder/decoder.

(b) Command byte insertion/detection.

(d) Cell scrambler/descrambler.

(e) HEC generation/verification.

• CPU interface: Intel or Motorola can be selected.

• Supports STP and UTP (Categories 3, 4, 5).

• Loopback function: Loopback in the PMD and ATM layers.

• Operation And Maintenance (OAM) functions: Input failure detection, HEC error detection and 4B/5B code error detection.

• Test function: Supports JTAG.

• Power supply voltage: 3.3 V ± 5 .