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UPD98414F2-RN1中文资料瑞萨数据手册PDF规格书

UPD98414F2-RN1
厂商型号

UPD98414F2-RN1

功能描述

MOS INTEGRATED CIRCUIT

文件大小

505.95 Kbytes

页面数量

46

生产厂商 Renesas Technology Corp
企业简称

RENESAS瑞萨

中文名称

瑞萨科技有限公司官网

原厂标识
数据手册

下载地址一下载地址二到原厂下载

更新时间

2025-5-20 20:00:00

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UPD98414F2-RN1价格和库存,欢迎联系客服免费人工找货

UPD98414F2-RN1规格书详情

FEATURES

• Supplies the functions of the TC (Transmission Convergence) sublayer recommended by the ATM Forum and

ITU-T.

• Supports the concatenation frame of 2.4 Gbps SONET STS-48c/SDH STM-16c.

• ATM layer interface

• 32-bit, 104-MHz LVTTL FIFO interface

• 15-cell transmit/receive FIFO

• Supports 52-byte/56-byte cell formats.

• Prefixes one-word TAG area to receive cell.

• Circuit side interface

• 16-bit PECL level I/O

• Either of two modes can be selected for CPU interface

• 16-bit data bus

• Intel-compatible mode [RD, WR, RDY-type]/Motorola-compatible mode [DS, R/W, ACK-type]

• Supports two types of overhead interfaces (that can access all overhead areas).

• Incorporates overhead byte insert/drop registers.

• Incorporates dedicated overhead byte insert/extract interfaces.

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