UPD98441F1-GA3-A中文资料瑞萨数据手册PDF规格书

FEATURES

• Parallel interface supporting packet and ATM cell with optimum mode selectable

• UTOPIA Level2 or POS-PHY Level2

• Master operation or slave operation

• 8-bit bus or 16-bit bus (52 MHz MAX.)

• Up to 124 ports can be connected in UTOPIA mode by combination of extension signal and port identifier.

Up to 32 ports can be connected in POS-PHY mode.

• Cell length selectable in range of 52 to 64 bytes

• General-purpose Mux/Demux mode bypassing UTOPIA/POS-PHY block supported (option mode)

• Two channels of standard LVDS driver/receiver interfaces

• Line rate of one channel: 640 to 880 Mbps. Throughput data of up to OC12 can be transferred.

• Redundant connection allowing one LVDS channel to operate as auxiliary channel supported

• On-chip PLL and clock data recovery circuit (CDR)

• Reference clock input at LVTTL or PECL level (64 to 88 MHz)

• Back pressure transmission function to prevent cell/packet loss. Flow control in port units preventing influence on throughput of other ports

• Mode setting and status check by register access via 8-bit MPU interface

• Two types of MPU interfaces selectable