TMS320VC5416中文资料数字信号处理器数据手册TI规格书

描述 Description

The TMS320VC5416 fixed-point, digital signal processor (DSP) (hereafter referred to as the 5416 unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.
Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. The device also includes the control mechanisms to manage interrupts, repeated operations, and function calls.

特性 Features

• Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
• 17- ×17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
• Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
• Data Bus With a Bus Holder Feature
• 128K × 16-Bit On-Chip RAM Composed of:
• Eight Blocks of 8K × 16-Bit On-Chip Single-Access Program RAM
• Enhanced External Parallel Interface (XIO2)
• Block-Memory-Move Instructions for Better Program and Data Management
• Instructions With Two- or Three-Operand Reads
• Conditional Store Instructions
• On-Chip Peripherals
• On-Chip Programmable Phase-Locked Loop (PLL) Clock Generator With External Clock Source
• Six-Channel Direct Memory Access (DMA) Controller
• 8/16-Bit Enhanced Parallel Host-Port Interface (HPI8/16)
• CLKOUT Off Control to Disable CLKOUT
• 144-Pin Ball Grid Array (BGA) (GGU Suffix)
• 6.25-ns Single-Cycle Fixed-Point Instruction Execution Time (160 MIPS)
• 3.3-V I/O Supply Voltage (160 and 120 MIPS)
• 1.5-V Core Supply Voltage (120 MIPS)
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. NOTE: This data manual is designed to be used in conjunction with the TMS320C54x™ DSP Functional Overview (literature number SPRU307). TMS320C54x, TMS320 are trademarks of Texas Instruments.