TMS320VC5402A中文资料定点数字信号处理器数据手册TI规格书

描述 Description

The TMS320VC5402A fixed-point, digital signal processor (DSP) (hereafterreferred to as the 5402A unless otherwise specified) is based on an advancedmodified Harvard architecture that has one program memory bus and three datamemory buses. This processor provides an arithmetic logic unit (ALU) with a highdegree of parallelism, application-specific hardware logic, on-chip memory, andadditional on-chip peripherals. The basis of the operational flexibility andspeed of this DSP is a highly specialized instruction set.
Separate program and data spaces allow simultaneous access to programinstructions and data, providing a high degree of parallelism. Two readoperations and one write operation can be performed in a single cycle.Instructions with parallel store and application-specific instructions can fullyutilize this architecture. In addition, data can be transferred between data andprogram spaces. Such parallelism supports a powerful set of arithmetic, logic,and bit-manipulation operations that can all be performed in a single machinecycle. The 5402A also includes the control mechanisms to manage interrupts,

特性 Features

• Advanced Multibus Architecture With Three Separate 16-Bit Data MemoryBuses and One Program Memory Bus
• 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter andTwo Independent 40-Bit Accumulators
• 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder forNon-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
• Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection ofthe Viterbi Operator
• Exponent Encoder to Compute an Exponent Value of a 40-Bit AccumulatorValue in a Single Cycle
• Two Address Generators With Eight Auxiliary Registers and Two AuxiliaryRegister Arithmetic Units (ARAUs)
• Data Bus With a Bus Holder Feature
• Extended Addressing Mode for 8M × 16-Bit Maximum Addressable ExternalProgram Space
• 16K x 16-Bit On-Chip RAM Composed of:
• 16K × 16-Bit On-Chip ROM Configured for Program Memory
• Enhanced External Parallel Interface (XIO2)
• Single-Instruction-Repeat and Block-Repeat Operations for Program Code
• Block-Memory-Move Instructions for Better Program and Data Management
• Instructions With a 32-Bit Long Word Operand
• Instructions With Two- or Three-Operand Reads
• Arithmetic Instructions With Parallel Store and Parallel Load
• Conditional Store Instructions
• Fast Return From Interrupt
• On-Chip Peripherals
• On-Chip Programmable Phase-Locked Loop (PLL) Clock Generator WithInternal Oscillator or External Clock Source
• Six-Channel Direct Memory Access (DMA) Controller
• Three Multichannel Buffered Serial Ports (McBSPs)
• 8/16-Bit Enhanced Parallel Host-Port Interface (HPI8/16)
• CLKOUT Off Control to Disable CLKOUT
• On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1
• (JTAG)Boundary Scan Logic
• 144-Pin Ball Grid Array (BGA)[GGU Suffix]
• 144-Pin Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
• 6.25-ns Single-Cycle Fixed-Point Instruction Execution Time (160 MIPS)
• 3.3-V I/O Supply Voltage
• 1.6-V Core Supply Voltage
• IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. NOTE: This data manual is designed to be used in conjunction with the TMS320C54x™ DSP Functional Overview (literature number SPRU307). TMS320C54x, BGA, C54x, TMS320C5000, C5000, TMS320 are trademarks of Texas Instruments.