TMS320VC5401中文资料定点数字信号处理器数据手册TI规格书

描述 Description

The TMS320VC5401 fixed-point, digital signal processor (DSP) (hereafter referred to as the 5401 unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.
Separate program and data spaces allow simultaneous access to program instructions and data, providing the high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can be performed in a single machine cycle. In addition, the 5401 includes the control mechanisms to manage interrupts, repeated operations, and function calls.

特性 Features

• Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
• 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
• Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
• Data Bus With a Bus-Holder Feature
• 4K x 16-Bit On-Chip ROM
• Single-Instruction-Repeat and Block-Repeat Operations for Program Code
• Instructions With a 32-Bit Long Word Operand
• Arithmetic Instructions With Parallel Store and Parallel Load
• Fast Return From Interrupt
• Software-Programmable Wait-State Generator and Programmable Bank Switching
• Two Multichannel Buffered Serial Ports (McBSPs)
• Two 16-Bit Timers
• Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes
• On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1 (JTAG) Boundary Scan Logic
• 144-Pin Plastic Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
• 144-Ball MicroStar BGA™ (GGU Suffix)
IEEE Standard 1149.1-1990 Standard Test-Access Port and Boundary Scan Architecture. TMS320C54x and MicroStar BGA are trademarks of Texas Instruments. All trademarks are the property of their respective owners