TMS320VC5410A中文资料数字信号处理器数据手册TI规格书

描述 Description

The TMS320VC5410A fixed-point, digital signal processor (DSP) (hereafter referred to as the 5410A unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.
Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. The 5410A also includes the control mechanisms to manage interrupts, repeated operations, and function calls.

特性 Features

• Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
• 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
• Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
• Data Bus With a Bus Holder Feature
• 64K x 16-Bit On-Chip RAM Composed of:
• 16K × 16-Bit On-Chip ROM Configured for Program Memory
• Single-Instruction-Repeat and Block-Repeat Operations for Program Code
• Instructions With a 32-Bit Long Word Operand
• Arithmetic Instructions With Parallel Store and Parallel Load
• Fast Return From Interrupt
• On-Chip Programmable Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source
• Six-Channel Direct Memory Access (DMA) Controller
• 8/16-Bit Enhanced Parallel Host-Port Interface (HPI8/16)
• CLKOUT Off Control to Disable CLKOUT
• (JTAG) Boundary Scan Logic
• 144-Pin Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
• 8.33-ns Single-Cycle Fixed-Point Instruction Execution Time (120 MIPS)
• 1.6-V Core Supply Voltage (160 MIPS)
• IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. NOTE: This data manual is designed to be used in conjunction with the TMS320C54x™ DSP Functional Overview (literature number SPRU307). TMS320C54x, MicroStar BGA, TMS320C54x, C54x, TMS320C5000, C5000, TMS320 are trademarks of Texas Instruments.