TMS320C6452中文资料C64x+ 定点 DSP- 高达 900MHz、1Gbps 以太网数据手册TI规格书

描述 Description

The TMS320C64x+™ DSPs (including the TMS320C6452 device is the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The C6452 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices.Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.With performance of up to 7200 million instructions per second (MIPS) at a clock rate of 900MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for up to 3600 million MACs per second (MMACS), or eight 8-bit MACs per cycle for up tp 8800 MMACS. For more details on the C64x+ DSP, see the (literature number SPRU732).The devices also have application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 256K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 1408KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.The device has a 1000 Mbps Ethernet Switch Subsystem with a management data input/output (MDIO) module and two SGMII ports; a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) bus interface; a multichannel audio serial port (McASP) with ten serializers; two telecom serial interface ports (TSIP); four 64-bit general-purpose timers each configurable as two independent 32-bit timers; a user-configurable 16-bit or 32-bit host-port interface (HPI); 32 pins for general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; one UART; and two glueless external memory interfaces: a synchronous and asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher DDR2 SDRAM interface.The management data input/output (MDIO) module continuously polls all 32 MDIO addresses to enumerate all PHY devices in the system.The I2C and VLYNQ ports allow the device to easily control peripheral modules and/or communicate with host processors. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.The devices have a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

特性 Features

• High-Performance Digital Media Processor
• 1.39 ns (-720), 1.11 ns (-900) Instruction Cycle Time
• Eight 32-Bit C64x+ Instructions/Cycle
• Commercial Temperature Ranges (-720, -900 only)
• VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
• Six ALUs (32-/40-Bit), Each Supports Single 32-bit, Dual 16-bit, or Quad 8-bit Arithmetic per Clock Cycle
• Load-Store Architecture With Non-Aligned Support
• Instruction Packing Reduces Code Size
• Additional C64x+™ Enhancements
• Exceptions Support for Error Detection and Program Redirection
• C64x+ Instruction Set Features
• 8-bit Overflow Protection
• Normalization, Saturation, Bit-Counting
• C64x+ Extensions
• Additional Instructions to Support Complex Multiplies
• C64x+ L1/L2 Memory Architecture
• 256K-bit (32K-byte) L1D Data RAM/Cache [2-Way Set-Associative]
• Supports Little Endian Mode Only
• 32-Bit DDR2 SDRAM Memory Controller With 512M-Byte Address Space (1.8-V I/O)
• Up to 128M-Byte Total Address Reach
• Glueless Interface to Asynchronous Memories (SRAM, Flash, and EEPROM)
• Supports Interface to Standard Sync Devices and Custom Logic (FPGA, CPLD, ASICs, etc.)
• Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
• Four 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
• One 4-wire Serial Port Interface (SPI) With Two Chip-Selects
• Two Telecom Serial Interface Ports (TSIP0/1)
• Ten Serializers and SPDIF (DIT) Mode
• 16/32-Bit Host-Port Interface (HPI)
• 32-Bit 33-/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.3
• On-Chip ROM Bootloader
• Flexible PLL Clock Generators
• 32 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
• 529-pin nFBGA (ZUT suffix)
• 0.09-µm/6-Level Cu Metal Process (CMOS)
• 3.3-V and 1.8-V I/O, 1.2-V Internal (-720,-900)