TMS320C6211B中文资料C62x 定点 DSP- 高达 167MHz数据手册TI规格书

描述 Description

The TMS320C62x™ DSPs (including the TMS320C6211/C6211B devices) compose one of the fixed-point DSP families in the TMS320C6000™ DSP platform. The TMS320C6211 (C6211) and TMS320C6211B (C6211B) devices are based on the high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications.

With performance of up to 1333 million instructions per second (MIPS) at a clock rate of 167 MHz, the C6211/C6211B device offers cost-effective solutions to high-performance DSP programming challenges. The C6211/C6211B DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6211/C6211B can produce two multiply-accumulates (MACs) per cycle for a total of 333 million MACs per second (MMACS). The C6211/C6211B DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The C6211/C6211B uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM and asynchronous peripherals.

The C6211/C6211B has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

特性 Features

• Excellent Price/Performance Digital Signal Processors (DSPs): TMS320C62x™ (TMS320C6211 and TMS320C6211B)
• C6211, C6211B, C6711, and C6711B are Pin-Compatible
• 6.7-, 6-ns Instruction Cycle Time
• Extended Temperature Device (C6211B)
• VelociTI™ Advanced Very Long Instruction Word (VLIW) C62x™ DSP Core (C6211/11B)
• Six ALUs (32-/40-Bit)
• Load-Store Architecture With 32 32-Bit General-Purpose Registers
• All Instructions Conditional
• Instruction Set Features
• 8-Bit Overflow Protection
• Bit-Field Extract, Set, Clear
• Normalization
• L1/L2 Memory Architecture
• 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative)
• Device Configuration
• Endianness: Little Endian, Big Endian
• 32-Bit External Memory Interface (EMIF)
• Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
• Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
• Access to Entire Memory Map
• Two Multichannel Buffered Serial Ports (McBSPs)
• ST-Bus-Switching Compatible
• AC97-Compatible
• Two 32-Bit General-Purpose Timers
• IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
• 0.18-µm/5-Level Metal Process
• 3.3-V I/Os, 1.8-V Internal
TMS320C62x, VelociTI, and C62x are trademarks of Texas Instruments. Motorola is a trademark of Motorola, Inc.

简介

TMS320C6211B属于集成电路（IC）的DSP（数字信号处理器）。由TI制造生产的TMS320C6211BDSP（数字信号处理器）数字信号处理器是类似于微处理器或微控制器的器件，但区别在于其内部架构经修改，适用于对连续数据流连续执行以乘法和加法运算为主的算法，而不是以条件逻辑或大量并发进程为主的算法。该器件通常用于诸如音频或视频信号处理等应用。