TMS320C6202B数据手册集成电路（IC）的DSP（数字信号处理器）规格书PDF

描述 Description

The TMS320C6202 and TMS320C6202B devices are part of the TMS320C62x™ fixed-point DSP generation in the TMS320C6000™ DSP platform. The C62x™ DSP devices are based on the high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications.

The TMS320C62x™ DSP offers cost-effective solutions to high-performance DSP-programming challenges. The TMS320C6202/02B has a performance capability of up to 2400 million instructions per second (MIPS) at 300 MHz. The C6202/02B DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. These processors have 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6202/02B can produce two multiply-accumulates (MACs) per cycle. This gives a total of 600 million MACs per second (MMACS) for the C6202/02B device. The C6202/02B DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The C6202/02B devices program memory consists of two blocks, with a 128K-byte block configured as memory-mapped program space, and the other 128K-byte block user-configurable as cache or memory-mapped program space. Data memory for the C6202/02B consists of two 64K-byte blocks of RAM.

The C6202/02B device has a powerful and diverse set of peripherals. The peripheral set includes three multichannel buffered serial ports (McBSPs), two general-purpose timers, a 32-bit expansion bus (XBus) that offers ease of interface to synchronous or asynchronous industry-standard host bus protocols, and a glueless 32-bit external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.

The C62x™ devices have a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

特性 Features

• High-Performance Fixed-Point Digital Signal Processors (DSPs) – TMS320C62x™
• 5-, 4-, 3.33-ns Instruction Cycle Time
• 200-, 250-, 300-MHz Clock Rate
• Eight 32-Bit Instructions/Cycle
• 1600, 2000, 2400 MIPS

• C6202 and C6203B GLS Ball Grid Array (BGA) Packages are Pin-Compatible With the C6204 GLW BGA Package
• C6202B and C6203B GNZ and GNY Packages are Pin-Compatible
• VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) C62x™ DSP Core
• Eight Highly Independent Functional Units:
• Six ALUs (32-/40-Bit)
• Two 16-Bit Multipliers (32-Bit Result)

• Load-Store Architecture With 32 32-Bit General-Purpose Registers
• Instruction Packing Reduces Code Size
• All Instructions Conditional

• Instruction Set Features
• Byte-Addressable (8-, 16-, 32-Bit Data)
• 8-Bit Overflow Protection
• Saturation
• Bit-Field Extract, Set, Clear
• Bit-Counting
• Normalization

• 3M-Bit On-Chip SRAM
• 2M-Bit Internal Program/Cache (64K 32-Bit Instructions)
• 1M-Bit Dual-Access Internal Data (128K Bytes)
• Organized as Two 64K-Byte Blocks for Improved Concurrency


• 32-Bit External Memory Interface (EMIF)
• Glueless Interface to Synchronous Memories: SDRAM or SBSRAM
• Glueless Interface to Asynchronous Memories: SRAM and EPROM
• 52M-Byte Addressable External Memory Space

• Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel
• Flexible Phase-Locked-Loop (PLL) Clock Generator
• 32-Bit Expansion Bus (XBus)
• Glueless/Low-Glue Interface to Popular PCI Bridge Chips
• Glueless/Low-Glue Interface to Popular Synchronous or Asynchronous Microprocessor Buses
• Master/Slave Functionality
• Glueless Interface to Synchronous FIFOs and Asynchronous Peripherals

• Three Multichannel Buffered Serial Ports (McBSPs)
• Direct Interface to T1/E1, MVIP, SCSA Framers
• ST-Bus-Switching Compatible
• Up to 256 Channels Each
• AC97-Compatible
• Serial-Peripheral Interface (SPI) Compatible (Motorola™)

• Two 32-Bit General-Purpose Timers
• IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
• 352-Pin BGA Package (GJL) (C6202)
• 352-Pin BGA Package (GNZ) (C6202B)
• 384-Pin BGA Package (GLS) (C6202)
• 384-Pin BGA Package (GNY) (C6202B)
• 0.18-µm/5-Level Metal Process (C6202)     0.15-µm/5-Level Metal Process (C6202B)
• CMOS Technology

• 3.3-V I/Os, 1.8-V Internal (C6202) 3.3-V I/Os, 1.5-V Internal (C6202B)
TMS320C62x, VelociTI, and C62x are trademarks of Texas Instruments. Motorola is a trademark of Motorola, Inc. Other trademarks are the property of their respective owners. For more details, see the GLS BGA package bottom view. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. TMS320C6000 is a trademark of Texas Instruments. C6000 is a trademark of Texas Instruments. Windows is a registered trademark of the Microsoft Corporation.