SY10H842中文资料Translators Products数据手册Microchip规格书

描述 Description

The SY10/100H842 are single supply, low skew translating 1:4 clock drivers.The devices feature a 24mA TTL output stage, with AC performance specified into a 50pF load capacitance. A HIGH on the enable pin (EN) forces all outputs LOW. As frequencies increase to 40MHz and above, precise timing and shaping of clock signals becomes extremely important. The H842 solves several clock distribution problems such as minimizing skew 300ps), maximizing clock fanout (24mA drive), and precise duty cycle control through a proprietary differential internal design.The 10K version is compatible with 10KH ECL logic levels. The 100K version is compatible with 100K levels.

特性 Features

·Translates positive ECL-to-TTL (PECL-to-TTL)
·300ps pin-to-pin skew
·500ps part-to-part skew
·Differential internal design for increased noise immunity and stable threshold inputs
·VBB reference output
·Single supply
·Enable input
·Extra TTL and ECL power/ground pins to reduce cross-talk/noise
·High drive capability: 24mA each output
·Fully compatible with industry standard 10K, 100K I/O levels
·Available in 16-pin SOIC package

简介

SY10H842属于集成电路（IC）的时钟缓冲器驱动器。由制造生产的SY10H842时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。