SY10EP51中文资料Flip Flops, Registers Products数据手册Microchip规格书

描述 Description

The SY10EP51V is a D flip-flop with reset and differential clock. The device is pin and functionally equivalent to the EL51 device.The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when CLK is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the CLK. The differential clock inputs of the EP51V allow the device to be used as a negative edge triggered flip-flop.The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to VEE and the /CLK input will be biased a VCC/2.

特性 Features

·3.3V and 5V power supply options
·320ps typical propagation delay
·Maximum frequency >3GHz typical
·75Ω internal input pulldown resistors
·Transistor count: 143
·Available in 8-Pin (3mm x 3mm) MSOP, SOIC and MLF®(2mm x 2mm) packages

简介

SY10EP51属于集成电路（IC）的触发器。由制造生产的SY10EP51触发器触发器是能够存储单个逻辑状态或信息“位”的基本数字存储器件。这些器件至少有两个输入；一个或多个用于传递要存储的数据，另一个用于指示存储该数据的时间点。不同的触发器类型，例如 D（延迟）、SR（置位复位）和 JK，对提供给其输入的信号有不同的响应，可用于实现不同的逻辑功能。这些器件与锁存器的不同之处在于它们是边缘敏感器件，其保持的逻辑状态仅在接收到有效时钟信号时才会改变。