SY10EP451中文资料Flip Flops, Registers Products数据手册Microchip规格书

描述 Description

The SY10/100EP451L is a 6-bit fully differential register with common clock and single-ended Master Reset (MR). It is ideal for very high frequency applications where a registered data path is necessary.All inputs have an internal 75kΩ pull-down resistor. Differential inputs have an override clamp. Unused differential register inputs can be left open and will default LOW. When the differential inputs are forced to a value smaller than VEE +1.2V, the clamp will override and force the output to a default state.The positive transition of CLK (pin 4) will latch the registers. Master Reset (MR) HIGH will asynchronously reset all registers forcing Q outputs to go LOW.

特性 Features

·450ps typical propagation delay
·Maximum frequency >3.0GHz typical
·Asynchronous Master Reset
·20ps skew within device, 35ps skew device-to-device
·PECL mode operating range: VCC = 3.0V to 3.6V with VEE = 0V
·NECL mode operating range: VCC = 0V with VEE = –3.0V to –3.6V
·Open input default state
·Safety clamp on inputs
·Available in 32-pin TQFP

简介

SY10EP451属于集成电路（IC）的触发器。由制造生产的SY10EP451触发器触发器是能够存储单个逻辑状态或信息“位”的基本数字存储器件。这些器件至少有两个输入；一个或多个用于传递要存储的数据，另一个用于指示存储该数据的时间点。不同的触发器类型，例如 D（延迟）、SR（置位复位）和 JK，对提供给其输入的信号有不同的响应，可用于实现不同的逻辑功能。这些器件与锁存器的不同之处在于它们是边缘敏感器件，其保持的逻辑状态仅在接收到有效时钟信号时才会改变。