Galvanically isolated 3 A single gate driver for Enhancement mode GaN FETs

Features • High voltage rail up to 1200 V • Driver current capability: 2 A / 3 A source/sink @25 °C, VH = 6 V • dV/dt transient immunity ±100 V/ns • Input-output propagation delay: 45 ns • Separate sink and source option for easy gate driving configuration • UVLO function optimized for GaN

文件：551.02 Kbytes 页数：20 Pages

STMICROELECTRONICS

意法半导体

丝印：GAP2GS；Package：SO-8；Galvanically isolated 3 A single gate driver for Enhancement mode GaN FETs

Features • High voltage rail up to 1200 V • Driver current capability: 2 A / 3 A source/sink @25 °C, VH = 6 V • dV/dt transient immunity ±100 V/ns • Input-output propagation delay: 45 ns • Separate sink and source option for easy gate driving configuration • UVLO function optimized for GaN

文件：551.02 Kbytes 页数：20 Pages

STMICROELECTRONICS

意法半导体

丝印：GAP2GS；Package：SO-8；Galvanically isolated 3 A single gate driver for Enhancement mode GaN FETs

Features • High voltage rail up to 1200 V • Driver current capability: 2 A / 3 A source/sink @25 °C, VH = 6 V • dV/dt transient immunity ±100 V/ns • Input-output propagation delay: 45 ns • Separate sink and source option for easy gate driving configuration • UVLO function optimized for GaN

文件：551.02 Kbytes 页数：20 Pages

STMICROELECTRONICS

意法半导体

Isolated 3 A single gate driver for Enhancement mode GaN FETs

Features • High voltage rail up to 1700 V • Driver current capability: 2 A / 3 A source/sink @25 °C, VH = 6 V • dV/dt transient immunity ±100 V/ns • Input-output propagation delay: 45 ns • Separate sink and source option for easy gate driving configuration • UVLO function optimized for GaN

文件：556.07 Kbytes 页数：20 Pages

STMICROELECTRONICS

意法半导体

丝印：GAP2GSN；Package：SO-8；Isolated 3 A single gate driver for Enhancement mode GaN FETs

Features • High voltage rail up to 1700 V • Driver current capability: 2 A / 3 A source/sink @25 °C, VH = 6 V • dV/dt transient immunity ±100 V/ns • Input-output propagation delay: 45 ns • Separate sink and source option for easy gate driving configuration • UVLO function optimized for GaN

文件：556.07 Kbytes 页数：20 Pages

STMICROELECTRONICS

意法半导体

丝印：GAP2GSN；Package：SO-8；Isolated 3 A single gate driver for Enhancement mode GaN FETs

Features • High voltage rail up to 1700 V • Driver current capability: 2 A / 3 A source/sink @25 °C, VH = 6 V • dV/dt transient immunity ±100 V/ns • Input-output propagation delay: 45 ns • Separate sink and source option for easy gate driving configuration • UVLO function optimized for GaN

文件：556.07 Kbytes 页数：20 Pages

STMICROELECTRONICS

意法半导体

电气隔离3 A单栅极驱动器，用于增强模式GaN FET

STGAP2GS是在栅极驱动通道与低压控制和接口电路之间提供电流隔离的单栅极驱动器。\n\n 该栅极驱动器具有2 A供电电流、3 A受电电流和轨到轨输出，使得该器件同样适用于工业应用中的功率转换、电机驱动逆变器等高功率应用。\n\n 该器件可以通过专用栅极电阻进行独立的导通和关断优化。\n\n 该器件集成了多种保护功能，包括热关断和UVLO，这些功能针对增强模式GaN FET进行了优化，可轻松帮助用户设计出高效可靠的系统。双输入引脚允许选择信号极性控制和实现HW联锁保护，以避免在控制器故障时发生交叉传导。\n\n 输入到输出的传播延迟在45 ns内，PWM控制精度高。\n\n 可以使用待机模式 • 高压导轨达1200 V \n• 驱动器电流能力：25 ℃条件下，2A/3A供电/受电电流，VH = 6 V \n• dV/dt瞬态抗扰度±100 V/ns \n• 输入到输出的传播延迟：45 ns \n• 独立的电流拉灌选项，轻松实现栅极驱动配置 \n• UVLO功能针对GaN进行优化• 栅极驱动电压高达15 V \n• 具有迟滞的3.3 V、5 V TTL/CMOS输入 \n• 温度关断保护 \n• 待机功能 \n• 宽体SO-8W封装;

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Isolated 3 A single gate driver for Enhancement mode GaN FETs

The STGAP2GSN is a single gate driver which provides isolation between the gate driving channel and the low voltage control and interface circuitry.\n\n The gate driver is characterized by 2 A source and 3 A sink capability and rail-to-rail outputs, making the device also suitable for mid and high p • High voltage rail up to 1700 V \n• Driver current capability: 2 A / 3 A source/sink @25 °C, VH = 6 V \n• dV/dt transient immunity ±100 V/ns \n• Input-output propagation delay: 45 ns \n• Separate sink and source option for easy gate driving configuration \n• UVLO function optimized for GaN• Gate dr;

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意法半导体