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SN74LS348N.A

丝印:SN74LS348N;Package:PDIP;8-LINE TO 3-LINE PRIORITY ENCODERS WITH 3-STATE OUTPUTS

3-State Outputs Drive Bus Lines Directly Encodes 8 Data Lines to 3-Line Binary (Octal) Applications Include: N-Bit Encoding Code Converters and Generators Typical Data Delay... 15 ns Typical Power Dissipation . . . 60 mW description These TTL encoders feature priority decoding of the in

文件:420.81 Kbytes 页数:9 Pages

TI

德州仪器

SN74LS373N

丝印:SN74LS373N;Package:PDIP;OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and

文件:1.58154 Mbytes 页数:32 Pages

TI

德州仪器

SN74LS373NE4

丝印:SN74LS373N;Package:PDIP;OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and

文件:1.58154 Mbytes 页数:32 Pages

TI

德州仪器

SN74LS374N

丝印:SN74LS374N;Package:PDIP;OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and

文件:1.58154 Mbytes 页数:32 Pages

TI

德州仪器

SN74LS374NE4

丝印:SN74LS374N;Package:PDIP;OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and

文件:1.58154 Mbytes 页数:32 Pages

TI

德州仪器

SN74LS375N

丝印:SN74LS375N;Package:PDIP;4.BIT BISTABLE LATCHES

Supply Voltage and Ground on Corner Pins To Simplify P-C Board Layout description The SN54LS376 and SN74LS376 bistable latches are electrically and functionally identical to the SN54LS75 and SN74LS75, respectively. Only the arrangement of the terminals hes been changed in the SN54L5375 an

文件:395.7 Kbytes 页数:9 Pages

TI

德州仪器

SN74LS375N.A

丝印:SN74LS375N;Package:PDIP;4.BIT BISTABLE LATCHES

Supply Voltage and Ground on Corner Pins To Simplify P-C Board Layout description The SN54LS376 and SN74LS376 bistable latches are electrically and functionally identical to the SN54LS75 and SN74LS75, respectively. Only the arrangement of the terminals hes been changed in the SN54L5375 an

文件:395.7 Kbytes 页数:9 Pages

TI

德州仪器

SN74LS38N

丝印:SN74LS38N;Package:PDIP;QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS WITH OPEN-COLLECTOR OUTPUTS

description These devices contain four independent 2-input NAND buffer gates with open-collector outputs. The open- collector outputs require pull-up resistors to perform correctly. They may be connected to other open- collector outputs to implement active-low wired-OR or active-high wired-A

文件:1.32219 Mbytes 页数:24 Pages

TI

德州仪器

SN74LS38NE4

丝印:SN74LS38N;Package:PDIP;QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS WITH OPEN-COLLECTOR OUTPUTS

description These devices contain four independent 2-input NAND buffer gates with open-collector outputs. The open- collector outputs require pull-up resistors to perform correctly. They may be connected to other open- collector outputs to implement active-low wired-OR or active-high wired-A

文件:1.32219 Mbytes 页数:24 Pages

TI

德州仪器

SN74LS399N

丝印:SN74LS399N;Package:PDIP;QUADRUPLE 2-INPUT MULTIPLEXERS WITH STORAGE

Single-Rail Outputs on ‘LS399 Selects One of Two 4-Bit Data Sources and Stores Data Synchronously with System Clock Applications: Dual Source for Operands and Constants in Arithmetic Processor; Can Release Processor Register Files for Acquiring New Data Implement Separate Registers Capabl

文件:384.92 Kbytes 页数:9 Pages

TI

德州仪器

技术参数

  • Supply voltage (Min) (V):

    4.75

  • Supply voltage (Max) (V):

    5.25

  • Number of channels (#):

    4

  • Inputs per channel:

    2

  • IOL (Max) (mA):

    8

  • IOH (Max) (mA):

    -0.4

  • Input type:

    Bipolar

  • Output type:

    Push-Pull

  • Features:

    High speed (tpd 10- 50ns)

  • Data rate (Max) (Mbps):

    35

  • Rating:

    Catalog

供应商型号品牌批号封装库存备注价格
TI
16+
SO-20
8000
原装现货请来电咨询
询价
TI
23+
DIP
7000
绝对全新原装!100%保质量特价!请放心订购!
询价
25+
DIP
18000
原厂直接发货进口原装
询价
TI
24+
NA
8
原装现货假一罚十
询价
TI
25+
SOP
2500
强调现货,随时查询!
询价
MOT
2016+
DIP
1950
只做原装,假一罚十,公司可开17%增值税发票!
询价
TI
13+
DIP-16
1283
原装分销
询价
TMS
06+
PDIP
1000
自己公司全新库存绝对有货
询价
SN
24+
SOP
20000
全新原厂原装,进口正品现货,正规渠道可含税!!
询价
TI
25+23+
5.2SOP14
25977
绝对原装正品全新进口深圳现货
询价
更多SN74LS供应商 更新时间2025-12-11 10:01:00