丝印：SN74LS174N；Package：PDIP；HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

“174, 'LS174, ‘S174 Contain Six Flip-Flops with Single-Rail Outputs ‘175, 'L.S175, ‘S175 Contain Four Flip-Flops with Double-Rail Outputs Three Performance Ranges Offered: See Table Lower Right Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications incl

文件：494.45 Kbytes 页数：16 Pages

TI

德州仪器

丝印：SN74LS174N；Package：PDIP；HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

“174, 'LS174, ‘S174 Contain Six Flip-Flops with Single-Rail Outputs ‘175, 'L.S175, ‘S175 Contain Four Flip-Flops with Double-Rail Outputs Three Performance Ranges Offered: See Table Lower Right Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications incl

文件：494.45 Kbytes 页数：16 Pages

TI

德州仪器

丝印：SN74LS175N；Package：PDIP；HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

“174, 'LS174, ‘S174 Contain Six Flip-Flops with Single-Rail Outputs ‘175, 'L.S175, ‘S175 Contain Four Flip-Flops with Double-Rail Outputs Three Performance Ranges Offered: See Table Lower Right Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications incl

文件：494.45 Kbytes 页数：16 Pages

TI

德州仪器

丝印：SN74LS175N；Package：PDIP；HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

“174, 'LS174, ‘S174 Contain Six Flip-Flops with Single-Rail Outputs ‘175, 'L.S175, ‘S175 Contain Four Flip-Flops with Double-Rail Outputs Three Performance Ranges Offered: See Table Lower Right Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications incl

文件：494.45 Kbytes 页数：16 Pages

TI

德州仪器

丝印：SN74LS175N；Package：PDIP；HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

“174, 'LS174, ‘S174 Contain Six Flip-Flops with Single-Rail Outputs ‘175, 'L.S175, ‘S175 Contain Four Flip-Flops with Double-Rail Outputs Three Performance Ranges Offered: See Table Lower Right Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications incl

文件：494.45 Kbytes 页数：16 Pages

TI

德州仪器

丝印：SN74LS194AN；Package：PDIP；4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS

Parallel Inputs and Outputs Four Operating Modes: Synchronous Parallel Load Right Shift Left Shift Do Nothing Pasitive Edge- Triggered Clocking Direct Overriding Clear

文件：537.82 Kbytes 页数：15 Pages

TI

德州仪器

丝印：SN74LS194AN；Package：PDIP；4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS

Parallel Inputs and Outputs Four Operating Modes: Synchronous Parallel Load Right Shift Left Shift Do Nothing Pasitive Edge- Triggered Clocking Direct Overriding Clear

文件：537.82 Kbytes 页数：15 Pages

TI

德州仪器

丝印：SN74LS19AN；Package：PDIP；SCHMITT-TRIGGER POSITIVE-NAND GATES AND INVERTERS WITH TOTEM-POLE OUTPUTS

Functionally and Mechanically Identical to ‘L813, ‘LS14. and ‘LS132, Respectively Improved Line-Receiving Characteristics P-N-P Inputs Reduce System Loading Excellent Noise Immunity with Typical Hysteresis of 0.8 V description Each circuit functions as a NAND gate or inverter, but beca

文件：784.18 Kbytes 页数：15 Pages

TI

德州仪器

丝印：SN74LS19AN；Package：PDIP；SCHMITT-TRIGGER POSITIVE-NAND GATES AND INVERTERS WITH TOTEM-POLE OUTPUTS

Functionally and Mechanically Identical to ‘L813, ‘LS14. and ‘LS132, Respectively Improved Line-Receiving Characteristics P-N-P Inputs Reduce System Loading Excellent Noise Immunity with Typical Hysteresis of 0.8 V description Each circuit functions as a NAND gate or inverter, but beca

文件：784.18 Kbytes 页数：15 Pages

TI

德州仪器

丝印：SN74LS240N；Package：PDIP；SNx4LS24x, SNx4S24x Octal Buffers and Line Drivers With 3-State Outputs

1 Features 1• Inputs Tolerant Down to 2 V, Compatible With 3.3-V or 2.5-V Logic Inputs • Maximum tpd of 15 ns at 5 V • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • PNP Inputs Reduce DC Loading • Hysteresis at Inputs Improves Noise Margins 2 Applications • Servers

文件：1.80212 Mbytes 页数：41 Pages

TI

德州仪器