3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

DESCRIPTION: The QS5LV919 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and design ensure

文件：98.35 Kbytes 页数：12 Pages

IDT

3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

DESCRIPTION: The QS5LV919 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and design ensure

文件：98.35 Kbytes 页数：12 Pages

IDT

SOT23-5

ROHM

罗姆

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SOT-25T

罗姆

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PLCC-2

onsemi / Fairchild

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