NDS352AP中文资料仙童半导体数据手册PDF规格书

General Description

These P -Channel logic level enhancement mode power field effect transistors are produced using Fairchilds proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as notebook computer power management, portable electronics, and other battery powered circuits where fast high-side switching, and low in-line power loss are needed in a very small outline surface mount package.

Features

■ -0.9 A, -30 V. RDS(ON) = 0.5 Ω @ VGS = -4.5 V

RDS(ON) = 0.3 Ω @ VGS = -10 V.

■ Industry standard outline SOT-23 surface mount package using proprietary SuperSOTTM-3 design for superior thermal and electrical capabilities.

■ High density cell design for extremely low RDS(ON).

■ Exceptional on-resistance and maximum DC current capability.