P-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchilds proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suit

文件：78.68 Kbytes 页数：6 Pages

Fairchild

仙童半导体

P-Channel Logic Level Enhancement Mode Field Effect Transistor

ONSEMI

安森美半导体

丝印：.39K；Package：SOT-23；P-Channel Mosfet

Application Load/Power Switching Interfacing Switching Logic Level Shift

文件：1.54866 Mbytes 页数：4 Pages

TECHPUBLIC

台舟电子

P-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchilds proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suit

文件：78.68 Kbytes 页数：6 Pages

Fairchild

仙童半导体

P-Channel Logic Level Enhancement Mode Field Effect Transistor

文件：456.46 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

P-Channel 20-V (D-S) MOSFET

文件：1.035609 Mbytes 页数：9 Pages

VBSEMI

微碧半导体

P 沟道逻辑电平增强型场效应晶体管，-20V，-1A，0.41Ω

这些P沟道逻辑电平增强模式功率场效应晶体管采用飞兆专有的高密度DMOS技术生产。 这种密度非常高的工艺是专为最大限度地降低通态电阻而定制的。 这些器件特别适合笔记本电脑电源管理、便携电子产品及其他电池供电电路等低电压应用，此类应用需要在很小尺寸的表面贴装封装中实现快速高端开关和低线内功率损耗。 •-1 A, -20 V, RDS(ON) = 0.41Ω @ VGS= -2.7 V, RDS(ON) = 0.3 Ω @ VGS = -4.5 V.\n•栅极驱动电平要求极低，从而可在3V电路中直接运行。 VGS(th) < 1.0V。\n•专有封装设计使用铜引线框架，可提供出色的热和电气能力。\n•高密度单元设计，可实现极低的RDS(ON)。\n•出色的导通阻抗和最大的DC电流能力。\n•紧凑型工业标准SOT-23表面贴装封装。;

ONSEMI

安森美半导体