P-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description These logic level P-Channel enhancement mode power field effect transistors are produced using Fairchilds proprietary, high cell density, DMOS technology. This very high density process has been especially tailored to minimize on-state resistance, provide superior switching pe

文件：62.15 Kbytes 页数：6 Pages

Fairchild

仙童半导体

P-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description These logic level P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process has been especially tailored to minimize on-state resistance, provide superior switching p

文件：167.43 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

isc P-Channel MOSFET Transistor

FEATURES ·Drain Current -ID= -24A@ TC=25℃ ·Drain Source Voltage -VDSS= -20V(Min) ·Static Drain-Source On-Resistance -RDS(on) = 50mΩ(Max)@VGS= 10V DESCRIPTION ·Motor drive, DC-DC converter, power switch and solenoid drive.

文件：344.29 Kbytes 页数：2 Pages

ISC

无锡固电

P 沟道，逻辑电平增强型场效应晶体管，-20V，-24A，50mΩ

这些逻辑电平P沟道增强模式功率场效应晶体管采用飞兆专有的高密度DMOS技术生产。 这种密度非常高的工艺是专为最大限度地降低通态电阻，提供卓越的开关性能，以及在雪崩和交换模式下承受高能量脉冲而定制的。 这些器件特别适合需要快速开关、低线路内功率损耗以及抗瞬变能力的汽车、DC/DC转换器、PWM电机控制和其他电池供电电路等低电压应用。 -24 A, -20 VrDS(ON) = 50 mΩ @ VGS = -4.5 VrDS(ON) = 70 mΩ @ VGS = -2.7 VrDS(ON) = 75 mΩ @ VGS = -2.5 V\nCritical DC Electrical Parameters Specified at Elevated Temperature\nRuggedInternal Source-Drain Diode Can Eliminate The Need For An External Zener Diode Transient Suppressor\n175°C Maximum Juncti;

ONSEMI

安森美半导体