NB3L8543S中文资料2.5 V/3.3 V Differential 2:1 MUX to 4 LVDS Clock Fanout Buffer Outputs with Clock Enable and Clock Select数据手册ONSEMI规格书

描述 Description

The NB3L8543S is a high performance, low skew 1−to−4 LVDS
Clock Fanout Buffer.
The NB3L8543S features a multiplexed input which can be driven
by either a differential or single−ended input to allow for the
distribution of a lower speed clock along with the high speed system
clock.
The CLK_SEL pin will select the differential CLK and CLKb inputs
when LOW (or left open and pulled LOW by the internal pull−down
resistor). When CLK_SEL is HIGH, the differential PCLK and PCLKb
inputs are selected.
The common clock enable pin, CLK_EN, is synchronous so that the
outputs will only be enabled/disabled when they are already in the
LOW state. This avoids any chance of generating a runt clock pulse on
the outputs during asynchronous assertion/deassertion of the clock
enable pin. The internal flip flop is clocked on the falling edge of the
input clock; therefore, all associated specification limits are
referenced to the negative edge of the clock input.

特性 Features

• Four Differential LVDS Output Pairs
• Two Selectable Differential Clock Inputs
• CLK/CLKb Can Accept LVPECL, LVDS, HCSL, HSTL and SSTL
• PCLK/PCLK Can Accept LVPECL, LVDS, CML and SSTL
• Maximum Output Frequency: 650 MHz
• Additive Phase Jitter, RMS: 50 fs (typical)
• Output Skew: 40 ps (maximum)
• Part−to−part Skew: 200 ps (maximum)
• Propagation Delay: 1.9 ns (maximum)

应用 Application

• Computing
• Telecom
• Backplanes
• Routers
• Servers
• Switches

简介

NB3L8543S属于集成电路（IC）的时钟缓冲器驱动器。由制造生产的NB3L8543S时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。