2.5 V/3.3 V Differential 2:1 MUX to 4 LVDS Clock Fanout Buffer Outputs

文件：234.16 Kbytes 页数：12 Pages

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2.5 V/3.3 V Differential 2:1 MUX to 4 LVDS Clock Fanout Buffer Outputs

文件：234.16 Kbytes 页数：12 Pages

ONSEMI

安森美半导体

2.5 V/3.3 V Differential 2:1 MUX to 4 LVDS Clock Fanout Buffer Outputs

文件：234.16 Kbytes 页数：12 Pages

ONSEMI

安森美半导体

2.5 V/3.3 V Differential 2:1 MUX to 4 LVDS Clock Fanout Buffer Outputs with Clock Enable and Clock Select

The NB3L8543S is a high performance, low skew 1−to−4 LVDS\nClock Fanout Buffer.\nThe NB3L8543S features a multiplexed input which can be driven\nby either a differential or single−ended input to allow for the\ndistribution of a lower speed clock along with the high speed system\nclock.\nThe CLK_SEL • Four Differential LVDS Output Pairs\n• Two Selectable Differential Clock Inputs\n• CLK/CLKb Can Accept LVPECL, LVDS, HCSL, HSTL and SSTL\n• PCLK/PCLK Can Accept LVPECL, LVDS, CML and SSTL\n• Maximum Output Frequency: 650 MHz\n• Additive Phase Jitter, RMS: 50 fs (typical)\n• Output Skew: 40 ps (max;

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Package：20-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 时钟缓冲器，驱动器 描述：IC CLK BUFF 2:1:4 LVPECL 20TSSOP

ONSEMI

安森美半导体

Package：20-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 时钟缓冲器，驱动器 描述：IC CLK BUFF 2:1:4 LVPECL 20TSSOP

ONSEMI

安森美半导体