NB3L8533中文资料2.5V/3.3V 差分，2:1 MUX - 4 LVPECL 扇出缓冲器数据手册ONSEMI规格书

描述 Description

The NB3L8533 is a low skew 1:4 LVPECL Clock fanout buffer designed explicitly for low output skew applications.
The NB3L8533 features a multiplexed input which can be driven by either a differential or single−ended input to allow for the distribution of a lower speed clock along with the high speed system clock.
The CLK_SEL pin will select the differential clock inputs, CLK and CLKb, when LOW (or left open and pulled LOW by the internal pull−down resistor). When CLK_SEL is HIGH, the Differential PCLK and PCLKb inputs are selected.
The common enable (CLK_EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state.
This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input.

特性 Features

• CLK/CLKb can Accept LVPECL, LVDS, HCSL, STTL and HSTL
• PCLK/PCLKb can Accept LVPECL, LVDS, CML and SSTL
• Four Differential LVPECL Clock Outputs
• 1.5 ns Maximum Propagation Delay
• LVCMOS Compatible Control Inputs
• Selectable Differential Clock Inputs
• Synchronous Clock Enable
• 30 ps Max. Skew Between Outputs
• 650 MHz Maximum Clock Output Frequency

应用 Application

• Backplanes
• Computing
• Telecom
• Routers
• Servers
• Switches

简介

NB3L8533属于集成电路（IC）的时钟缓冲器驱动器。由制造生产的NB3L8533时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。