NB3L202K数据手册开发板套件编程器的评估演示板及套件规格书PDF

描述 Description

The NB3L202K is a differential 1:2 Clock fanout buffer with
High−speed Current Steering Logic (HCSL) outputs. Inputs can
directly accept differential LVPECL, LVDS, and HCSL signals.
Single−ended LVPECL, HCSL, LVCMOS, or LVTTL levels are
accepted with a proper external Vth reference supply per Figures 4
and 6. The input signal will be translated to HCSL and provides two
identical copies operating up to 350 MHz.
The NB3L202K is optimized for ultra−low phase noise, propagation
delay variation and low output–to–output skew, and is DB200H
compliant. As such, system designers can take advantage of the
NB3L202K’s performance to distribute low skew clocks across the
backplane or the motherboard making it ideal for Clock and Data
distribution applications such as PCI Express, FBDIMM, Networking,
Mobile Computing, Gigabit Ethernet, etc.
Output drive current is set by connecting a 475 \u0002 resistor from
IREF (Pin 10) to GND per Figure 11. Outputs can also interface to
LVDS receivers when terminated per Figure 12.

特性 Features

• Maximum Input Clock Frequency > 350 MHz
• 2.5 V ±5% / 3.3 V ±10% Supply Voltage Operation
• 2 HCSL Outputs
• DB200H Compliant
• Individual OE Control Pin for Each Bank of Outputs
• 100 ps Max Output−to−Output Skew Performance
• 1 ns Typical Propagation Delay
• 500 ps Typical Rise and Fall Times
• 80 fs Maximum Additive Phase Jitter RMS
• PCIe Gen 3 and Gen 4 Compliant

应用 Application

• Mobile Computing
• Networking
• Gigabit Ethernet
• FBDIMM
• PCI Express Gen 3 and Gen 4

简介

NB3L202K属于开发板套件编程器的评估演示板及套件。由制造生产的NB3L202K评估和演示板及套件该系列产品提供了一种方便的方法，在经过验证的实施环境中评估某些重点器件的性能或特性。评估方法通常有完善的文档说明，并且视乎具体情况由评估软件提供支持。产品通常由印刷电路板组成，板上已装有重点器件以及必要或有用的支持元器件，另外也可能包括其他组件，例如电缆或电源。对于数量特别多或类别独特的器件类别(如 ADC、DAC 和开关模式电源)，评估平台可组合为一个单独的产品系列。