NB2304A中文资料Zero Delay Buffer, 3.3 V, Quad Output数据手册ONSEMI规格书

描述 Description

The NB2304A is a versatile, 3.3 V zero delay buffer designed to distribute high-speed clocks. It accepts one reference input and drives out four low-skew clocks. It is available in a 8 pin package. The -1H version of the NB2304A operates at up to 133 MHz, and has higher drive than the -1 devices. All parts have on-chip PLLs that lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. Multiple NB2304A devices can accept the same input clock and distribute it. In this case the skew between the outputs of the two devices is guaranteed to be less than 700 ps. All outputs have less than 200 ps of cycle-to-cycle jitter. The input and output propagation delay is guaranteed to be less than 250 ps, and the output to output skew is guaranteed to be less than 200 ps. The NB2304A is available in two different configurations, as shown in the ordering information table. The NB2304AI is the base part. The NB2304AI1H is the high drive version of the -1 and its rise and fall times are much faster than -1 part.

特性 Features

• 15 MHz to 133 MHz Operating Range, Compatible with CPU and PCI Bus
• Zero Input - Output Propagation Delay
• Multiple Low-Skew Outputs
• Output-Output Skew Less than 200 ps
• Device-Device Skew Less than 700 ps
• One Input Drives 4 Outputs
• Less than 200 ps Cycle-to-Cycle Jitter is Compatible with Pentium Based
• Available in 8 Pin, 150 mil SOIC Package
• 3.3 V Operation, Advanced 0.35CMOS Technology
• Pb-Free Packages
• High-Speed clock distribution in PC, workstation, datacom, and telecom
• Precision clock synchronization

应用 Application

• DIMM or PCI bus clocking

简介

NB2304A属于集成电路（IC）的时钟发生器PLL频率合成器。由制造生产的NB2304A时钟发生器，PLL，频率合成器时钟发生器、PLL 和频率合成器集成电路 (IC) 可为逻辑器件提供参考信号的稳定定时脉冲，这些器件包括计算机、微控制器、数据通信系统和图形/视频发生器。这些集成电路可能包括缓冲器、驱动器、分频器、倍频器、多路复用器、合成器、扇出分配器和预分频器。