Dual J-K Flip-Flop with Reset

Dual J-K Flip-Flop with Reset High–Performance Silicon–Gate CMOS The MC74HC73 is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip flop is negative–edge clocked and has an active

文件：170.82 Kbytes 页数：5 Pages

Motorola

摩托罗拉

Dual J-K Flip-Flop with Reset

文件：91.06 Kbytes 页数：7 Pages

ONSEMI

安森美半导体

Dual J-K Flip-Flop with Reset

文件：91.06 Kbytes 页数：7 Pages

ONSEMI

安森美半导体

Dual J-K Flip-Flop with Reset

文件：91.06 Kbytes 页数：7 Pages

ONSEMI

安森美半导体

Dual J-K Flip-Flop with Reset

文件：91.06 Kbytes 页数：7 Pages

ONSEMI

安森美半导体

Dual J-K Flip-Flop with Reset

文件：91.06 Kbytes 页数：7 Pages

ONSEMI

安森美半导体

Dual J-K Flip-Flop with Reset

文件：91.06 Kbytes 页数：7 Pages

ONSEMI

安森美半导体

Dual JK Flip Flop with Reset

High Performance Silicon Gate CMOS. The MC74HC73A is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs, with pullup resistors, they are compatible with LSTTL outputs. Each flip flop is negative edge clocked and has an active low asynchronous reset. The MC74 • Output Drive Capability: 10 LSTTL Loads\n• Outputs Directly Interface to CMOS, NMOS, and TTL\n• Operating Voltage Range: 2.0 to 6.0 V\n• Low Input Current: 1.0 µA\n• High Noise Immunity Characteristic of CMOS Devices\n• In Compliance with the JEDEC Standard No. 7.0 A Requirements\n• Chip Complexit;

ONSEMI

安森美半导体

Dual J-K Flip-Flop with Reset

Dual J-K Flip-Flop with Reset\nHigh–Performance Silicon–Gate CMOSThe MC74HC73 is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.\nEach flip flop is negative–edge clocked and has an active–low

恩XP

恩智浦

Package：14-SOIC（0.154"，3.90mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 功能：复位 类别：集成电路（IC） 触发器 描述：IC FF JK TYPE DUAL 1BIT 14SOIC

ONSEMI

安森美半导体