MC100EPT21中文资料LVPECL/LVDS/CML 到 LVTTL/LVCMOS 差分转换器数据手册ONSEMI规格书

描述 Description

The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL/LVDS/CML input levels and LVTTL/LVCMOS output levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package makes the EPT21 ideal for applications which require the translation of a clock or data signal. The VBB output allows the EPT21 to be cap coupled in either single-ended or differential input mode. When single-ended cap coupled, VBB output tied to the D0 input for a non-inverting buffer or the D0 input for an inverting buffer. When cap coupled differentially, VBB output is connected through a resistor to each input pin. If used, the VBB pin should be bypassed to VCC via a 0.01 F capacitor. For additional information see AND8020. For a single-ended direct connection use an external voltage reference source such as a resistor divider. Do not use VBB for a single-ended direct connection.

特性 Features

• 1.4ns Typical Propagation Delay
• Maximum Frequency > 275 MHz Typical
• 24mA TTL outputs
• LVPECL/LVDS/CML Inputs, LVTTL/LVCMOS Outputs
• The 100 Series Contains Temperature Compensation
• VBB Output
• New Differential Input Common Mode Range

应用 Application

• Precision Clock Translation

简介

MC100EPT21属于集成电路（IC）的转换器电平移位器。由制造生产的MC100EPT21转换器，电平移位器逻辑转换器或电平移位器 IC 可用于在数字逻辑设备之间传递信息，这些设备可在不同/不兼容的供电电压下工作，或可实现不同的信令方式。例如，可以将需要 5 V 电源的数字输出传感器连接到具有 3.3 V I/O 电源的 FPGA，或者在 CMOS 或 TTL 等单端信令方式与 PECL 或 LVDS 等差分技术之间进行转换。