3.3V / 5VECL Differential Receiver/Driver with High Gain

Description The EP16VA is a world−class differential receiver/driver. The device is functionally equivalent to the EP16 and LVEP16 devices but with high gain output. QHG and QHG outputs have a DC gain several times larger than the DC gain of an EP16. The VBB pin, an internally generated volt

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3.3V / 5VECL Differential Receiver/Driver with High Gain

Description The EP16VA is a world−class differential receiver/driver. The device is functionally equivalent to the EP16 and LVEP16 devices but with high gain output. QHG and QHG outputs have a DC gain several times larger than the DC gain of an EP16. The VBB pin, an internally generated volt

文件：77.45 Kbytes 页数：8 Pages

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3.3V / 5V ECL Quad Differential Driver/Receiver

3.3V / 5V ECL Quad Differential Driver/Receiver Description The MC10/100EP17 is a 4-bit differential line receiver based on the EP17 device. The >3.0 GHz maximum frequency provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators. The VBB pin, an

文件：83.48 Kbytes 页数：8 Pages

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3.3V / 5V ECL Quad Differential Driver/Receiver

3.3V / 5V ECL Quad Differential Driver/Receiver Description The MC10/100EP17 is a 4-bit differential line receiver based on the EP17 device. The >3.0 GHz maximum frequency provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators. The VBB pin, an

文件：83.48 Kbytes 页数：8 Pages

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3.3V / 5V ECL Quad Differential Driver/Receiver

3.3V / 5V ECL Quad Differential Driver/Receiver Description The MC10/100EP17 is a 4-bit differential line receiver based on the EP17 device. The >3.0 GHz maximum frequency provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators. The VBB pin, an

文件：83.48 Kbytes 页数：8 Pages

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3.3V / 5V ECL Quad Differential Driver/Receiver

3.3V / 5V ECL Quad Differential Driver/Receiver Description The MC10/100EP17 is a 4-bit differential line receiver based on the EP17 device. The >3.0 GHz maximum frequency provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators. The VBB pin, an

文件：83.48 Kbytes 页数：8 Pages

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3.3V ECL Programmable Delay Chip

The MC10/100EP195 is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The 100 Series contains temperature compensation. • Maximum Input Clock Frequency >1.2 GHz Typical • Progra

文件：127.14 Kbytes 页数：20 Pages

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Clock Management Design Using Low Skew and Low Jitter Devices

Why Do We Need Clock Management? Can you imagine the chaos in our world if our clocks or watches were not synchronized to Greenwich Mean Time? How would trains, buses, and airplanes run on schedule? The miniseries Longitude was the story of a man who made a major technological breakthrough by inv

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3.3V ECL Programmable Delay Chip

The MC10/100EP195 is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The 100 Series contains temperature compensation. • Maximum Input Clock Frequency >1.2 GHz Typical • Progra

文件：127.14 Kbytes 页数：20 Pages

ONSEMI

安森美半导体

3.3V ECL Programmable Delay Chip

The MC10/100EP195 is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The 100 Series contains temperature compensation. • Maximum Input Clock Frequency >1.2 GHz Typical • Progra

文件：127.14 Kbytes 页数：20 Pages

ONSEMI

安森美半导体