MC100EP195FAR2集成电路（IC）的延迟线规格书PDF中文资料

MC100EP195FAR2属于集成电路（IC）的延迟线。由安森美半导体制造生产的MC100EP195FAR2延迟线时钟延迟线产品族中的产品属于数字器件，用于在数字信号中引入时间延迟，以便将提交给器件输入的信号跃迁，经过某一已知时间之后在输出端复现。它们常用于高速数字系统，以校正或补偿不同信号路径之间的信号传播时间的偏差。这些器件可用于产生固定、可选或可变持续时间的延迟。

The MC10/100EP195 is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition.

The 100 Series contains temperature compensation.

• Maximum Input Clock Frequency >1.2 GHz Typical

• Programmable Range: 0 ns to 10 ns

• Delay Range: 2.2 ns to 12.2 ns

• 10 ps Increments

• PECL Mode Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V

• NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −3.6 V

• Open Input Default State

• Safety Clamp on Inputs

• A Logic High on the EN Pin Will Force Q to Logic Low

• D[10:0] Can Accept Either ECL, LVCMOS, or LVTTL Inputs

• VBB Output Reference Voltage

• Pb−Free Packages are Available