MBM29LV017数据手册Fujitsu中文资料规格书

描述 Description

■ GENERAL DESCRIPTION
The MBM29LV017 is a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each. The 2M bytes of data is divided into 32 sectors of 64K bytes of flexible erase capability. The 8 bits of data will appear on DQ0 to DQ7. The MBM29LV017 is offered in a 40-pin TSOP (I), 48-ball FBGA packages. The device is designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers.■ FEATURES
• Address specification is not necessary during command sequence
• Single 3.0 V read, program and erase
   Minimizes system level power requirements
• Compatible with JEDEC-standard commands
   Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
   40-pin TSOP (I) (Package suffix: PTN-Normal Bend Type, PTR-Reversed Bend Type)
   48-ball FBGA (Package suffix: PBT)
• Minimum 100,000 program/erase cycles
• High performance
   80 ns maximum access time
• Sector erase architecture
   Uniform sectors of 64K bytes each Any combination of sectors can be concurrently erased. Also supports full chip erase
• Embedded EraseTM Algorithms
   Automatically pre-programs and erases the chip or any sector
• Embedded programTM Algorithms
   Automatically programs and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
   Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
   When addresses remain stable, automatically switches themselves to low power mode
• Low VCC write inhibit ≤ 2.5 V
• Hardware RESET pin
   Resets internal state machine to the read mode
• Erase Suspend/Resume
   Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector protection
   Hardware method disables any combination of sectors from program or erase operations
• Sector Protection set function by Extended sector protect command
• Temporary sector unprotection
   Temporary sector unprotection via the RESET pin
• In accordance with CFI (Common Flash Memory Interface)

特性 Features

• Address specification is not necessary during command sequence
• Single 3.0 V read, program and erase
   Minimizes system level power requirements
• Compatible with JEDEC-standard commands
   Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
   40-pin TSOP (I) (Package suffix: PTN-Normal Bend Type, PTR-Reversed Bend Type)
   48-ball FBGA (Package suffix: PBT)
• Minimum 100,000 program/erase cycles
• High performance
   80 ns maximum access time
• Sector erase architecture
   Uniform sectors of 64K bytes each Any combination of sectors can be concurrently erased. Also supports full chip erase
• Embedded EraseTM Algorithms
   Automatically pre-programs and erases the chip or any sector
• Embedded programTM Algorithms
   Automatically programs and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
   Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
   When addresses remain stable, automatically switches themselves to low power mode
• Low VCC write inhibit ≤ 2.5 V
• Hardware RESET pin
   Resets internal state machine to the read mode
• Erase Suspend/Resume
   Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector protection
   Hardware method disables any combination of sectors from program or erase operations
• Sector Protection set function by Extended sector protect command
• Temporary sector unprotection
   Temporary sector unprotection via the RESET pin
• In accordance with CFI (Common Flash Memory Interface)