MBM29F016A-12数据手册Fujitsu中文资料规格书

描述 Description

■ GENERAL DESCRIPTION
The MBM29F016A is a 16 M-bit, 5.0 V-Only Flash memory organized as 2 M bytes of 8 bits each. The 2 M bytes of data is divided into 32 sectors of 64 K bytes for flexible erase capability. The 8 bit of data will appear on DQ0 to DQ7. The MBM29F016A is offered in a 48-pin TSOP(I) package. This device is designed to be programmed in-system with the standard system 5.0 V VCC supply. A 12.0 V VPP is not required for program or erase operations. The device can also be reprogrammed in standard EPROM programmers.■ FEATURES
• Single 5.0 V read, write, and erase
   Minimizes system level power requirements
• Compatible with JEDEC-standard commands
   Pinout and software compatible with single-power supply Flash
   Superior inadvertent write protection
• 48-pin TSOP(I) (Package Suffix: PFTN-Normal Bend Type, PFTR-Reverse Bend Type)
• Minimum 100,000 write/erase cycles
• High performance
   70 ns maximum access time
• Sector erase architecture
   Uniform sectors of 64 K bytes each
   Any combination of sectors can be erased. Also supports full chip erase.
• Embedded Erase™ Algorithms
   Automatically pre-programs and erases the chip or any sector
• Embedded Program™ Algorithms
   Automatically programs and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
   Hardware method for detection of program or erase cycle completion
• Low VCC write inhibit ≤ 3.2 V
• Hardware RESET pin
   Resets internal state machine to the read mode
• Erase Suspend/Resume
   Supports reading or programming data to a sector not being erased
• Sector group protection
   Hardware method that disables any combination of sector groups from write or erase operation (a sector group consists of 4 adjacent sectors of 64 K bytes each)
• Temporary sector groups unprotection
   Temporary sector unprotection via the RESET pin

特性 Features

• Single 5.0 V read, write, and erase
   Minimizes system level power requirements
• Compatible with JEDEC-standard commands
   Pinout and software compatible with single-power supply Flash
   Superior inadvertent write protection
• 48-pin TSOP(I) (Package Suffix: PFTN-Normal Bend Type, PFTR-Reverse Bend Type)
• Minimum 100,000 write/erase cycles
• High performance
   70 ns maximum access time
• Sector erase architecture
   Uniform sectors of 64 K bytes each
   Any combination of sectors can be erased. Also supports full chip erase.
• Embedded Erase™ Algorithms
   Automatically pre-programs and erases the chip or any sector
• Embedded Program™ Algorithms
   Automatically programs and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
   Hardware method for detection of program or erase cycle completion
• Low VCC write inhibit ≤ 3.2 V
• Hardware RESET pin
   Resets internal state machine to the read mode
• Erase Suspend/Resume
   Supports reading or programming data to a sector not being erased
• Sector group protection
   Hardware method that disables any combination of sector groups from write or erase operation (a sector group consists of 4 adjacent sectors of 64 K bytes each)
• Temporary sector groups unprotection
   Temporary sector unprotection via the RESET pin