MBM29LV002BC-12数据手册Fujitsu中文资料规格书

描述 Description

■ GENERAL DESCRIPTION
The MBM29LV002TC/BC are a 2M-bit, 3.0 V-only Flash memory organized as 256K bytes of 8 bits each. The MBM29LV002TC/BC are offered in a 40-pin TSOP(I) and 40-pin SON packages. These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers.■ FEATURES
• Single 3.0 V read, program, and erase
   Minimizes system level power requirements
• Compatible with JEDEC-standard commands
   Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
   40-pin TSOP(I) (Package suffix: PTN – Normal Bend Type, PTR – Reversed Bend Type)
   40-pin SON (Package suffix: PNS)
• Minimum 100,000 program/erase cycles
• High performance
   70 ns maximum access time
• Sector erase architecture
   One 16K byte, two 8K bytes, one 32K byte, and three 64K bytes
   Any combination of sectors can be concurrently erased. Also supports full chip erase
• Boot Code Sector Architecture
   T = Top sector
   B = Bottom sector
• Embedded EraseTM Algorithms
   Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM Algorithms
   Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
   Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
   When addresses remain stable, automatically switch themselves to low power mode
• Low VCC write inhibit ≤ 2.5 V
• Erase Suspend/Resume
   Suspends the erase operation to allow a read data in another sector within the same device
• Sector protection
   Hardware method disables any combination of sectors from program or erase operations
• Sector Protection Set function by Extended sector protection command
• Temporary sector unprotection
   Temporary sector unprotection via the RESET pin

特性 Features

• Single 3.0 V read, program, and erase
   Minimizes system level power requirements
• Compatible with JEDEC-standard commands
   Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
   40-pin TSOP(I) (Package suffix: PTN – Normal Bend Type, PTR – Reversed Bend Type)
   40-pin SON (Package suffix: PNS)
• Minimum 100,000 program/erase cycles
• High performance
   70 ns maximum access time
• Sector erase architecture
   One 16K byte, two 8K bytes, one 32K byte, and three 64K bytes
   Any combination of sectors can be concurrently erased. Also supports full chip erase
• Boot Code Sector Architecture
   T = Top sector
   B = Bottom sector
• Embedded EraseTM Algorithms
   Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM Algorithms
   Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
   Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
   When addresses remain stable, automatically switch themselves to low power mode
• Low VCC write inhibit ≤ 2.5 V
• Erase Suspend/Resume
   Suspends the erase operation to allow a read data in another sector within the same device
• Sector protection
   Hardware method disables any combination of sectors from program or erase operations
• Sector Protection Set function by Extended sector protection command
• Temporary sector unprotection
   Temporary sector unprotection via the RESET pin